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I have some Ethernet issues with a set of boards (6/10 are bad). They're possibly just assembly house mistakes... but I'm very concerned about my magnetics jack.

I could have sworn I saw a example schematic with my jack's topology used with my PHY before, but I can't find it. The PHY's datasheet and suggested magnetics jacks are all identical in topology, and very different than what I have.

I'm using a SMSC LAN8720AI PHY, with a Bel SI-52003-F magnetics jack. The transformer ratios on my jack vs. a suggested jack for this PHY like the SI-60152-F are the same (1:1). The inductance is the same, 350uH. However, the choke on mine is on the circuit side, not network side. Also, while the TLA has four 75 ohm resistors from taps tied to a single 1nF/2kV cap, mine has an extra set of 1nF caps between the taps and the 75 ohm resistors.

The main difference is that my jack is a POE jack, and I thought I found an example that used one exactly like it. So, the topology is obviously different just because of that feature.

At the moment, I have 4 good boards, 1 'sometimes' board, and 5 boards that just blink a LED at 11.68Hz representing some error that no datasheet explains.

How important is this? Of course there's no other jack with that footprint.

EDIT

I added some detail on the magnetics jacks above. I was just recommended the SI-60152-F, so I'll compare to that one. Of course like all the other recommendations... it also has no stock at anyone on FindChips.

LATE EDIT

It turns out my problem was the crystal layout that fed the Ethernet PLL. On the respin, I went with a more standard non-POE jack.

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Ethernet magnetics do vary, in particular in turns ratio between the network and circuit sides, and other parameters like center taps and baluns. The ethernet signalling voltages are well defined, but some PHYs operate at different voltages. Since ethernet is transformer coupled, that's no problem since the transformer can be built with any turns ratio. The PHY then also has to operate at the right impedance so that it comes out to the ethernet impedance of 50 Ω at the network side. The only way to know what your PHY wants is to look at its datasheet. PHY datasheets should tell you what transformer ratio they require.

POE versus not is mostly a issue of providing center taps on the network side. Transformers can also vary in whether they include a balun (common mode choke) on the network side or not. Note that this also makes the transformer so that it has a network side and a circuit side. Even with 1:1 ratio you shouldn't flip it around since the balun is pointless on the circuit side. The purpose of the balun is to keep high frequencies that might be present on the board from leaking out via the cable and therefore emitting too much RF.

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  • \$\begingroup\$ I added more detail. the choke on mine is swapped to the circuit side relative to the recommended one. I also have some extra caps in series with the termination resistors. Not optimal, or not going to work? I'll change the design for the next set of boards... but I'd like to get these first ones working and in people's hands. \$\endgroup\$ – darron Sep 29 '11 at 23:14
  • \$\begingroup\$ could you take a quick look at the two jacks mentioned above and tell me if you think 52003 I'm using is incompatible? I've got the choke flipped to the circuit side and extra caps on the network side. \$\endgroup\$ – darron Oct 4 '11 at 16:29
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You mentioned PoE. I've seen an issue where quickly unplugging and re-inserting a PoE device fried the PHY chips because there were no proper protection diodes. A lot of PHY datasheets (that I've seen so far) don't mention this.

Microchip has a nice appnote (AN2157) on this issue. In short, you must have diodes on both sides of the RX and TX differential pairs to the PHY. This is a (very) basic schematic of what's shown in Figure 1 of the Microchip appnote.

schematic

simulate this circuit – Schematic created using CircuitLab

I know you said you already fixed this issue, but for future folks with PoE in their design, I hope this is useful.

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