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I have an Altera DE2 board that outputs a 50 MHz clock and I'm trying to write a verilog module that can bring it down to 1 Hz. How can I do this?


marked as duplicate by Brian Drummond, PeterJ, Daniel Grillo, Andy aka, Leon Heller Nov 26 '15 at 13:32

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    \$\begingroup\$ Divide by 50 million? \$\endgroup\$ – Andy aka Nov 26 '15 at 11:56
  • \$\begingroup\$ @rogerrowland I saw that question before I posted mine but I didn't understand most of the answer so I figured I'd ask it again to get simpler answers. \$\endgroup\$ – ninesalt Nov 26 '15 at 12:03
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    \$\begingroup\$ @Swailem95 It would have been useful to add the link to that question in your question and to explain what it was you didn't understand. Just hoping that asking a dupe will get you a "simpler" answer is a bit of a gamble. \$\endgroup\$ – Roger Rowland Nov 26 '15 at 12:07

It's pretty simple, we just need to build a big counter. We want our output clock to be 50 million times slower than our input clock. To generate a complete output cycle we need to toggle the output twice. Therefore we want to toggle the output every 25 million cycles.

In general the best type of counter to use for this sort of thing is a "count down to zero" counter. We will count down through the range from 24999999 (one less than 25 million) to zero, then repeat. Each time our counter hits zero we toggle the output. Our counter needs to be at least 25 bit to accomodate this range of values.

reg [24:0] counter;
output reg clkout;
input clkin
initial begin
    counter = 0;
    clkout = 0;
always @(posedge clkin) begin
    if (counter == 0) begin
        counter <= 24999999;
        clkout <= ~clkout;
    end else begin
        counter <= counter -1;
  • \$\begingroup\$ Why 25 million? Also what does the line right after the if statement do? \$\endgroup\$ – ninesalt Nov 26 '15 at 12:26
  • \$\begingroup\$ Does my edit answer your questions? \$\endgroup\$ – Peter Green Nov 26 '15 at 12:36
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    \$\begingroup\$ Why don't you learn some Verilog? \$\endgroup\$ – Leon Heller Nov 26 '15 at 13:33
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    \$\begingroup\$ It's a nonblocking assignment. I think you need to get yourself a basic verilog book and work through it. \$\endgroup\$ – Peter Green Nov 26 '15 at 13:36
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    \$\begingroup\$ It is worth mentioning that the constants should really be declared as 25bit wide as well, e.g. 25'd24999999 and counter <= counter - 25'd1. This is really just to avoid compiler warnings about truncation of signals. \$\endgroup\$ – Tom Carpenter Nov 26 '15 at 14:46

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