I have a ZC706 board equipped with a Zynq 045 FPGA. I switched the jumpers to add the Zynq into the JTAG chain of th Digilent programmer. The first programming works as expected, but the second programming does not alter the FPGA configuration.

When I run a full power cycle on the complete board, I can program the FPGA again, but no third time ...

Why can't I program a ZC706 board a second time over JTAG? Does the ARM lock the internal configuration FSM?

The "Done" LED stays always high so iMPACT doesn't notice a programming failure!

My task is to port a design from KC705 onto the ZC706. The hardware test example needs no ARM - this will be implemented by others :).

  • 1
    \$\begingroup\$ I'm using microZed. I always do a jtag boot of linux so I have the same problem. I just reset the processor before reload. I don't have an answer, just similiar experience \$\endgroup\$
    – johnnymopo
    Nov 27, 2015 at 4:21
  • \$\begingroup\$ @johnnymopo By reset, do you mean the reset button? \$\endgroup\$
    – Paebbels
    Nov 27, 2015 at 9:25
  • \$\begingroup\$ Yes. I think the FSBL (in my case) is responsible for loading the bitstream, so the processor must stop or reset before JTAG can work. You could probably issue a command to stop the processor. As I'm using linux and don't want to reset my terminal, I just "reboot" before a new upload. Are you using SDK to load bitstream? \$\endgroup\$
    – johnnymopo
    Nov 27, 2015 at 15:54
  • \$\begingroup\$ I have nothing loaded into the ARM, I think it's booting from Flash. There is no SD-Card in the slot. I'm using the plain JTAG interface from the Digilent programmer to upload my bit-file to the FPGA part of the Zynq. \$\endgroup\$
    – Paebbels
    Nov 27, 2015 at 18:57
  • \$\begingroup\$ I understand but what are using to talk to the cable. zedboard.org/content/zedboard-programming-zynq-impact shows an example using Impact that should work repeatedly \$\endgroup\$
    – johnnymopo
    Nov 27, 2015 at 19:03

1 Answer 1


It seems that the PS can lock the external PROG_B pin and the JPROGRAM JTAG instruction. The relevant bit is PCFG_PROG_B in devcfg.CTRL (address 0xF8007000, bit 30).

With a locic analyzer, I can see that Vivado sets this bit before programming the FPGA. I don't know how to get IMPACT to do the same, but you could probably have the ARM part execute a small program to set the bit.


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