# FIFO for spartan 3AN : no storage on board but ok in simulation

I made a FIFO using the Core Generator and I'm trying to implement a code that use it...

1) By putting the switch (T9) ON, I start transmitting some datas to my fifo (Here H-e-l-l-o for test)

2) By pressing the button T16, I read the FIFO

The code is working on simulation but not in implementation... Here's my simulation result :

The lines are in this order :

1. CLK
2. SWITCH
3. BUTTON
4. RST
5. No need
6. No need
7. No need
8. Data_out

As you can see, it sends a zero then a 72 (H from ASCII code because I'm sending data using RS232) then 101 (e) then 2 times 108 (l) and then 111 (0) is reapeted because the fifo is working in a way that if it's empty, it's sending the last value so it's working fine.

Here's the result I have using putty (an RS232 reader) and by pushing the button T16 a lot of times :

Here's a part of my code, I can put the zip file if you needed, just ask it in comment.

The part where I generate the data into the FIFO :

process(clk)
begin
if rising_edge (clk) then
if SW_T9 ='1' then
if cnt = 10 then
wr_en <= '0';
elsif cnt = 11 then
DATA <= "010010000000000000";--H
elsif cnt = 12 then
wr_en <= '1';
elsif cnt = 13 then
wr_en <= '0';
elsif cnt = 14 then
DATA <= "011001010000000000";--e
elsif cnt = 15 then
wr_en <= '1';
elsif cnt = 16 then
wr_en <= '0';
elsif cnt = 17 then
DATA <= "011011000000000000";--l
elsif cnt = 18 then
wr_en <= '1';
elsif cnt = 19 then
wr_en <= '0';
elsif cnt = 20 then
DATA <= "011011000000000000";--l
elsif cnt = 21 then
wr_en <= '1';
elsif cnt = 22 then
wr_en <= '0';
elsif cnt = 23 then
DATA <= "011011110000000000";--o
elsif cnt = 24 then
wr_en <= '1';
elsif cnt = 25 then
wr_en <= '0';
end if;
if cnt <25 then
cnt <= cnt+1;
end if;
end if;
end if;
end process;
end Behavioral;


Here are my errors (only during Synthesis) :

WARNING:Xst:2211 - "D:/Users/.../TOP_MODULE.vhd" line 135: Instantiating black box module .

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

WARNING:Xst:1710 - FF/Latch (without init value) has a constant value of 0 in block . This FF/Latch will be trimmed during the optimization process.

No important warning as you can see (I hope I'm right)...

My question is : Do you know why I don't have the same result in simulation and on board?

Don't hesitate to comment and ask me question, it's really important for me to solve this problem...

• Is the switch debounced? Does the design meet timing? Have you looked at the RTL output to verify the design compiles to something sensible (and that those warnings aren't removing important bits)? – Tom Carpenter Nov 27 '15 at 15:03
• I can debounce it quickly, I made it before but I forgot for this one... What do you mean by "Does the design meet timing?" and yes, the design compiles to something sensible and the warnings aren't removing important bits. Thanks for the quick answer – Cabs Nov 27 '15 at 15:06
• FPGAs can only run at some Fmax (maximum frequency) due to delays. The longer any combinational logic path, the slower this frequency. You need to add timing constraints (at the very least a clock definition) to the design to the ISE what frequency each clock runs at. The final stage of compilation is running what Xilinx calls "static timing verification". This will tell you if the design can run at the speed of your clock. If it can't you end up with all sorts of odd glitches. – Tom Carpenter Nov 27 '15 at 15:25
• Ok I don't see anything wrong in the static timing verification... Just to see, I made the same code but divided the clk and it works the same way (only oooooo trough my RS232...). I'll make a debouncer and see... Do you have any other idea? Thanks – Cabs Nov 27 '15 at 16:17