# FPGA Frequency divider with linear regulation

I'm currently developing an FPGA gateware requiring a regulated frequency divider and I wonder if there is any tricky way to get a linear output frequency regulation?

What I mean is that if I use a simple preloaded counter I get a f~1/x relevance, where x is a counter initial value. As I need to regulate frequency in a relatively wide range (say 0.5Hz-10kHz) I'd like it to be a linear function of some argument (of course, not necessarily a counter value-it can be something more complex ;-) ).

• It is linear function of 1/x, as you said. So what is the question? Nov 27 '15 at 17:10
• I know it is. But notice that change of one value of x in case of small values gives large changes in frequency. Whereas change in large values gives little change. I wounder if there is a method that gives more uniform changes in function of parameter. Nov 27 '15 at 18:15
• This is a nature of mathematics, you can't fight it. .Frequencies are generated by digital devices using timers, which by their nature can only count time, which is in the denominator. You can use some analog circuitry to overcome this limitation. Nov 27 '15 at 18:25
• Most FPGAs have at least one PLL that will give you more linear control. Nov 27 '15 at 18:33
• Are you wanting PLL or DDS? Nov 27 '15 at 19:34

At the moment, you are considering using a preloaded counter. This means that each clock cycle you get a fixed increment, in a variable accumulator length that you control, hence the frequency is reciprocal to your control value.

If instead you use a controllable variable increment in a fixed accumulator length, your frequency will be linearly dependent on the control value.

This is how a DDS works. A fixed length accumulator, typically a power of 2, for instance an 18 bit accumulator that counts up to 2^18 (250k-ish long) is incremented each clock cycle odf the system clock. In pigHDL, you would write

int count [17 downto 0];
process(on sys_clock rising):
_ count <= count+freq;
_ output := count[17];

This may, or may not, give you what you need. The MSB of the counter will give you the output, but unless freq is an exact power of 2, the output cycles will not be exactly the same length, they will vary by one count.

The average output frequency = freq * fs / accumulator length.

You can get increased resolution for the frequency by increasing the length of accumulator and frequency word, to the right.

There is no way to remove this one cycle jitter, if you are going to use the clock as a digital source. Bear in mind that for an FPGA, it is bad form to take the MSB output and use it as the clock line to other elements. Much better to turn it into a one cycle ClockEnable, and use that to condition the clock into downstream elements.

If it's for an external source, you can take the top several bits of the accumulator into a DAC, filter the waveform, and use a comparator, this will reduce the jitter considerably.

I will suggest using a binary rate multiplier. I have attached a reference sheet that shows what I mean. You can accurately use the binary multiplication to get a good range of output frequencies. Not exactly linear, but easily controlled.