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In my digital electronics project I need to calculate dot product of two vectors a and b (256 length of each). Following the basic concept, I need to calculate \$ \sum_{k=1}^{256} a_kb_k \$. Each element of vectors is 4-bit binary number. This doesn't seems to a difficult task in verilog where I can implement this as in XILINX ISE.

sum=0;

for(i=0,i<256,i=i+1)

sum=sum+ \$a_ib_i \$

Furthur I need to implement this on FPGA. But here I got confused in two concept:

  1. Do I need to write the module for 'full adder' and added the inputs previous sum and \$a_i b_i\$ bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.

  2. Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.

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    \$\begingroup\$ Loops and HDL do not go hand in hand. Forget everything you know about procedural programming languages and start thinking in RTL. \$\endgroup\$ Nov 28, 2015 at 18:40
  • \$\begingroup\$ What Xilinx tool? Xilinx is a company with many tools: ISE, Vivado, DSP tools, HLS, ... If you implement your dot-product in a loop it will synthesize but the clock frequency will be in the low MHz or kHz range! So you will need pipelining which need manual clock control / hand written HDL code. \$\endgroup\$
    – Paebbels
    Nov 28, 2015 at 18:55
  • \$\begingroup\$ @TomCarpenter I agree with you that I need to implement at RTl level. But do need to added the two 4-bit number bit by bit or xilinx will do it by '+' sign. \$\endgroup\$
    – Virange
    Nov 28, 2015 at 18:56
  • \$\begingroup\$ @Paebbels It's ISE. \$\endgroup\$
    – Virange
    Nov 28, 2015 at 19:01
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    \$\begingroup\$ Also, Verilog uses 0 indexing, so that for loop (which you shouldn't use) would be for(i=0;i<256;i=i+1) \$\endgroup\$ Nov 28, 2015 at 19:03

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Do I need to write the module for 'full adder' and added the inputs previous sum and aibi bit by bit and store output in sum. Or simply xilinx will automatically implement the full adder during synthsize.

You can expect any decent verilog synthesis tool to handle addition and subtraction operators. Most modern ones will also handle multiplication operators. Support for division operators is less common (and when they are implemented they tend to synthisize to very large slow blocks).

Most of the time it's fine to just use the addition, subtraction and multiplication operators. For really big adders and multipliers it is sometimes nessacery to break them up into smaller units to meet timing.

Is it valid to use for loop insted of writing always@(condition) beacause on FPGA we have clock as a control signal. Or in this case also xilinx itself will implement/control the for loop by clock signal.

synthesis tools will not turn a loop like that into sequential logic. Instead they will attempt to unroll it and implement it combinatorially. The result will be something that is both very big and very slow.

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