I've looked at the most popular flip-flop types, and none of them seem to have this desired behaviour:

It would have two inputs: A set signal, S, and a data signal, D.

If the set signal is true, it would save whatever is in the data input. However, if the set signal is false, nothing would change.

Let Q be the current saved bit.

This would be the truth table:

S D Q(next)

0 0 Q

0 1 Q

1 0 0

1 1 1

I've managed to reproduce this behaviour using a JK-flip-flop, two AND-gates and one OR-gate. Wouldn't this be particularly useful in computers? If so, why is there no such flip-flop (I may be wrong here)?


3 Answers 3


If this device has a clock, it's a D Flip-Flop with Enable.

If there is no clock, it's known as a "Gated" D-Latch. (https://en.wikipedia.org/wiki/Flip-flop_(electronics)#Gated_D_latch)

  • \$\begingroup\$ Of which [first kind] there are plenty e.g. 74HC377. However the enable pin is usually shared on such arrays in practice. \$\endgroup\$
    – Fizz
    Nov 28, 2015 at 23:28

The simplest way to get that behavior is to use a multiplexer:


simulate this circuit – Schematic created using CircuitLab

Such a circuit is known as a transparent latch rather than an edge-triggered flip-flop. When the S input is high, it transparently passes the D input to the output, and when the S input goes low, the output retains its state at that moment.

Yes, they're quite useful in computer and other circuits. See the 74xx75, and compare it to the ubiquitous 74xx74. 74xx373 and 74xx374 are 8-bit examples.


Another term is "latch" or "transparent latch", used in contrast to an edge-triggered D flip-flop, or register. As examples, contrast the edge-triggered 74374 with the transparent latch 74373 ICs Note the truth tables for the two varieties at the top of page 3.

In the earliest days of microcomputers, latches were commonly used on bus address lines, with an ALE (address latch enable), which would allow an address to be captured for the maximum amount of time by setting the latch line high during the expected transition period. The alternative, edge-triggering, requires that the clock be issued after the worst-case settling time for the addresses.


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