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It's been a very long time since I took intro level EE courses. I'm working on a hobby project and as a refresher I figured I would simulate a CMOS inverter. For the life of me I can't figure out why the simulation doesn't produce the expected results.

I believe I've faithfully reproduced the circuit from Wikipedia. I've wired it so the drains of the two MOSFETs are tied together. The source of the P-MOSFET is tied to the positive voltage. The source of the N-MOSFET is tied to ground.

I ran a simulation that stepped the gate voltage from 0V DC to 1.5V DC. The spec sheet for the MOSFETs say that their threshold voltage is in the range of 0.3V DC to 0.8V DC. The simulation showed pretty much no change in the output voltage. I re-ran the simulation from 0V DC to 12V DC and it produced the graph below.

Why is it that the output voltage doesn't change rapidly in the range of the threshold voltage of the MOSFETs? I was expecting it to drop from 12V DC to 0V DC very rapidly after the gate voltage exceeded 0.3V DC.

The Circuit

Circuit

Vout, Vmax as a Function of Vgate Over the Range 0V DC to 12V DC

Analysis

Vmax is the green line

Vout is the black line

Vgate is the blue line

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  • \$\begingroup\$ Looks right to me. "Digital" is just an interpretation of what is, at its most fundamental, an analog circuit. \$\endgroup\$ Commented Nov 30, 2015 at 7:54

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I'm just going answer one part of your question that I don't think anybody has answered head-on yet.

Why is it that the output voltage doesn't change rapidly in the range of the threshold voltage of the MOSFETs?

Say you have 1.5 V on Vgate. Now the NMOS is fully turned on, because you've exceeded the threshold voltage.

But what's Vgs of the PMOS?

It's still -10.5 V, also far in excess of the threshold voltage.

You have to drive Vgate up to near 11 V before the PMOS Vgs gets near its threshold voltage.

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  • \$\begingroup\$ I see. The driver for Vgate can't reach 12V in real life. It's logic level is 5V. I may have to consider an alternative approach. I seem to remember OpAmps working as inverting amplifiers. Maybe I can make that work. \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 4:03
  • \$\begingroup\$ @Huckle -- There are PFET's with lower thresholds. It seems Photon and I both believe that this specific model of a PFET has a higher threshold. An OpAmp without external feedback can work (it's called a comparator if you use it that way), but it will use a lot more power and may not be able to work fully 0-5V due to "headroom". It will also be slower (ceteris paribus). \$\endgroup\$ Commented Dec 1, 2015 at 22:08
  • \$\begingroup\$ @DrFriedParts, My point isn't about whether the PFET threshold is higher or lower. It's that you have to measure the PFET Vgs relative to VDD (where the source is connected) and not relative to ground. \$\endgroup\$
    – The Photon
    Commented Dec 2, 2015 at 1:27
  • \$\begingroup\$ @Photon Sure, but his concern/confusion seems to be over the absolute value being too large for his system rails and concluding no FET-based inverter could ever work... ergo he should try OpAmp(?). Anyway, that was my read of his comment. \$\endgroup\$ Commented Dec 2, 2015 at 4:20
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Unfortunately the MCH models given out by ON are not directly usable with LTspice (and I lack the patience/time to make them work tonight), so here's a substitute simulation with discrete, long-channel FETs, which still have pretty low thresholds:

enter image description here

The curve looks just as shitty/slow as yours. Also note the gigantic shoot-through current (hundreds of amps) that will blow the FETs off in real life.

Now look at a real CMOS gate done with short-channel FETs, which are only found in ICs (as far as I know):

enter image description here

The transition looks much sharper and the current while having the same shape is in micropampere range. The latter files are from http://ecee.colorado.edu/~ecen4827/spice.html The library included there is for some BSIM3.3 model.

So yeah, you got the schematic right, but not the process/FET details that make a workable CMOS gate. Also note in that 0.35um sim that the two FETs are not mere twins. They have different geometries in a CMOS inverter to get the midpoint right. To actually set the midpoint see p. 150 here. If you change the pmos there to W=3u (to "match" the nmos), the curve moves to the left and starts to look a bit like the discrete version (but the transition remains sharp).

enter image description here

Also textbook material:

Transistor current drive in the saturated state for submicron technologies is not quadratic but linear. It is dominated by carrier velocity saturation (vmax),

I = WCox(VDD – Vt)vmax

And given your not very clearly expressed expectations, you want to review how a CMOS inverter actually works:

enter image description here

Region I. nMOS off, pMOS ohmic.

Region II. nMOS saturated, pMOS ohmic.

Region III. nMOS saturated, pMOS saturated.

Region IV. nMOS ohmic, pMOS saturated.

Region V. nMOS ohmic, pMOS off.

These quotes and figure are from Segura and Hawkins CMOS textbook.

Also, it's possible to make CMOS gates with long-channel FETs, but textbooks tend not to cover this much anymore... I think you'd still need different geometries for the two transistors.


For amusement purposes only: Here is (totally ridiculous) way to get something more symmetrical with discretes (since we can do nothing about the geometry): use two p-channel mosfets in parallel on the high side (this is basically a way to double the width)!

enter image description here

Of course this does nothing to fix the lazy curve. To actually fix that you nee to pick a an appropriate Vdd for these MOSFETs, which depends on their thresholds. Here's an experiment varying Vdd:

enter image description here

You can see that at much lower Vdd voltage (given their low thresholds) these MOSFETs start to look more promising. In a real CMOS design, this of course done backwards: the transistors are designed with a Vdd (range) in mind.

And here we go, we'd made a 3v MOSFET gate (who needs Intel anymore?? :p). I would still not try this in practice, except with very disposable MOSFETs. We are exceeding the static current rating on those (which is 5A), but we're within the pulse current rating (30A). If the drive pulse is not fast enough though... bam.

enter image description here

Actually you can get something just as good with just one PMOS at this low voltage (the 6407 part is 5A while the 6408-part is 7A). Probably if you find some complementary pair that is closer it will look even better in terms of symmetry. I've just cut one of the pmos legs in the schematic below; that's on purpose.

enter image description here

If you limit Vdd to 2.5V, it would even look sensible even with respect to their static current limit (for these parts). I'm not gonna paste another graph here though. What I am going to add is a graph of a CD4000-series inverter, just so you see how much less power that uses (tens of milliamps at most). Goes to show that using power/trench mosfets to make a CMOS gate is still a very silly idea.

enter image description here

Alas TI doesn't give a FET model for those chips, but someone reverse-engineered (traced) them: http://people.rit.edu/lffeee/CD4007_SPICE_MODEL.pdf

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  • \$\begingroup\$ I actually only have access to CD4007UBE but the online simulator I found didn't have one in their catalog and importing a spice model didn't help because that tool only allows attachment of 3 terminal models to their transistor element. \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 4:44
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    \$\begingroup\$ I think the real misunderstanding I had was that I thought I didn't need to drive the gate voltage all the way to the upper rail. I thought anything beyond the N-MOS threshold was sufficient (I was only thinking about the N side of the circuit). Since I want to drive the gate voltage with a GPIO pin with a 5V logic level and need the output to be 0V..12V, it pretty much rules out CMOS (by itself at least). \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 4:47
  • \$\begingroup\$ I think I will try instead to use an OpAmp. If I remember correctly (probably not, it's been a while) OpAmps also don't sink a lot of current on the input side. I can pick the amplification to get my 5V driver up near the 12V I need. I don't think OpAmps get all the way to the rails though (or at least not the ones I have access to). Do you see a problem with that approach? \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 4:52
  • \$\begingroup\$ Here's what I'm thinking. I need to validate that the currents into and out of the circuit work for my purpose. imgur.com/a/Wn27n \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 5:38
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    \$\begingroup\$ @Huckle: Ah, an XY problem. What you actually want is called a level shifter. Either an opamp or there's a CD4000-series level shifter too. ti.com/lit/ds/symlink/cd40109b.pdf You might want to ask separately about that. In fact a comparator would be better than an opamp here. \$\endgroup\$ Commented Dec 1, 2015 at 11:15
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Your FET models are wrong...

The transistor parameters embedded in the SPICE deck are not the 0.3/0.8 VDC you think it is. If you dig into the simulation code (the spice deck) you will see this.

...but your simulation is not!

  1. Compare the input to output curves' slopes and you will notice there is at least a 10x gain occurring.
  2. Your input function is a forced linear ramp, meaning your simulator is running with input = 0.1V, then again with input = 0.2V, etc. It's showing the full transfer function. In a practical application, the input is driven with a step edge (to avoid meta-stability) and so you would skip the middle region as a fast transition at the input --> fast transition at the output as your simulation shows! :)
  3. It also shows that you get a full 12V for any input below 2.5V and 0V for any input above 8.5V. That's the inverting logic of a NOT gate and it shows the generally large noise immunity of CMOS logic (greater than 2.5V of noise tolerance for the end states in this case!).
  4. The transfer function is non-linear as expected.

So...

Your expectations are correct and you modelled it correctly! Good job! :)

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  • \$\begingroup\$ Actually they are. He just doesn't understand what threshold voltage means. \$\endgroup\$ Commented Nov 30, 2015 at 10:13
  • \$\begingroup\$ I was not expecting a "digitally" sharp curve. I expected there would be an S curve from high to low. I just expected the domain to be on the order of a volt. The driver for Vgate can only reach 5V. \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 4:00
  • \$\begingroup\$ @Huckle -- You have an S curve; it is just distorted. The distortion in the S is occurring because your NFET and PFET are not balanced (the NFET has significantly lower channel resistance). You would need to improve the channel width of your PFET to compensate for the almost 2x lower hole mobility. \$\endgroup\$ Commented Dec 1, 2015 at 22:05
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Your supply is 12V and you tried putting 1.5V on the gate connection. Well, with 0V on the gate connection the P channel FET will be fully turned on and the N channel will be off. With a volt on the gate, the P channel will be fully turned on (still) and the N channel will be starting to be turned on.

At this point you'll have a few (or maybe tens) of mA flowing through both transistors. If you put half the supply voltage (6V) on the gate, both devices would be fairly well turned on and you might have several amps flowing.

Is this really what you want to do?

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  • \$\begingroup\$ I see. The driver for Vgate can't reach 12V in real life. It's logic level is 5V. I may have to consider an alternative approach. I seem to remember OpAmps working as inverting amplifiers. Maybe I can make that work. \$\endgroup\$
    – Huckle
    Commented Dec 1, 2015 at 4:08
  • \$\begingroup\$ State what you are actually trying to achieve instead of describing potential solutions. \$\endgroup\$
    – Andy aka
    Commented Dec 1, 2015 at 9:17
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The behaviour you expect doesn't correspond to a simple inverter, but to an inverting Schmitt Trigger. Its CMOS implementation is more complex (example), additional components essentially create hysteresis which prevents the output gates from being both open at the same time, which is when CMOS logic consumes most power.

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