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I used some online calculator to calculate parameters of trace so it has 50 Ohm impedance.

I use FR-4, so H=1.5mm, T=0.035mm and Er = 4.5. 2-side PCB, one side with signals, the other with GND. I set the calculator to "microstrip" and for this data it told me to make trace width = 2.73 mm...

That's more than 100mils for width, most of my traces have 8-10 mils. I'm connecting DRAM to uC, there's no possibility I can me those traces so wide.

So how people achieve 50 Ohm impedance with reasonable traces width?

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    \$\begingroup\$ Use a multilayer board. then you can get H=0.25 mm or so. \$\endgroup\$ – The Photon Nov 30 '15 at 18:14
  • \$\begingroup\$ You'll want this. \$\endgroup\$ – Matt Young Nov 30 '15 at 18:15
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    \$\begingroup\$ I just covered this sort of in a previous post. The answer is correct, you can make the board thinner or look at planar wave guides. electronics.stackexchange.com/questions/202224/… \$\endgroup\$ – MadHatter Nov 30 '15 at 18:29
  • \$\begingroup\$ I have to use 2-side PCB... So ok, I can order a thiner PCB, like 1mm or 0.8mm. But: 1) Will it be good idea to leave traces without soldermask so they will be covered with solder (in HAL method) and thus the T parameter will be greater and impdance smaller (closer to 50 Ohm)? 2) But this will increase capacitance, right? So it's not really good for fast signals? 3) Besides, how really important is this impedance matching? I mean, starting with what frequency, does this matter? 4) Where can I find more about those "planar wave guides" - Google doesn't really help. \$\endgroup\$ – zupazt3 Nov 30 '15 at 19:03
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    \$\begingroup\$ If it is regular old SDRAM with approximately 25mm trace lengths, you probably don't need to worry about trace impedance. The rise and fall times will probably be at least 1 ns. You should try to keep solid GND under all SDRAM traces and under the SDRAM part itself. Add extra clearance all around the clock trace. \$\endgroup\$ – mkeith Dec 1 '15 at 1:13
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DRAM will NEVER work with transmission lines and terminations because the termination (50 ohms) will kill the digital signal.

The whole point about memory and micro slumming it in the same place (or very close) is that you can get away with teminations because the length of the trace is so short.

25mm of trace represents a signal delay of about 150p seconds and a rule of thumb is that you invert the 150ps to get a frequency of 6.7 GHz then divide that by ten to get an acceptable top limit speed for clk and data i.e. 670 MHz.

Is this too low?

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  • \$\begingroup\$ It's far more than I need. Besides, max. frequency of FMC controller in uC is 90MHz, so it's maximum of what I can get. So what do you say? I don't need to care about impedance matching? Or what? And what do you mean by "DRAM will NEVER work with transmission lines"? \$\endgroup\$ – zupazt3 Nov 30 '15 at 21:26
  • \$\begingroup\$ Hm..Not sure I agree/understand when you say that dram will never work with transmission lines because the termination resistor kills the digital signal. Do you have any evidence or material on this ? \$\endgroup\$ – efox29 Nov 30 '15 at 21:57
  • \$\begingroup\$ @efox29 - what will a CMOS output look like feeding a transmission line with a 50 ohm terminator? There's a case for having an output resistor in the driving circuit feeding a t-line with the t-line open circuited at the receive end but, any old t-line will do this and not a 50 ohm one. Think about the power dissipation of all those 50 ohm resistors on address and data lines - 2V (TTL high) across 50 ohms is a current of 40mA or maybe 20mA on average. Multiply this by the address and data bus widths and you have a hot circuit. \$\endgroup\$ – Andy aka Nov 30 '15 at 22:20
  • \$\begingroup\$ @zupazt3 - Did I say you "don't need to care about impedance matching?". No I didn't, I gave you information pertinant to your question and no other question. To reiterate - don't bother worrying about implementing transmission lines if the highest frequency has a wavelength of one tenth of the line length. In your case 90MHz could be regarded as having a highest frequency of the 5th harmonic i.e. 450 MHz so it's probably OK. \$\endgroup\$ – Andy aka Nov 30 '15 at 22:24
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    \$\begingroup\$ The point is, the load is not terminated at 50 Ohms, so what difference does it make if the transmission line is 100 Ohms or even more? Not much. Besides, the rise and fall times are probably much longer than the time it takes for the reflection to get back to the source. So, don't worry about the trace impedance. I have seen 133 MHz SDRAM work with 25mm "sky wires" attached to all the address lines (because somebody pin-swapped the address bits, LOL). Don't worry about it. \$\endgroup\$ – mkeith Dec 1 '15 at 1:18

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