The most convenient form of amplifier for use in a gate - because it has high input impedance and useful voltage gain - happens to be inverting. This is true whether it is a BJT (common emitter) or FET (common source) amplifier.
Thus a gate formed of a single amplifier stage MUST have an inverting output - that means it can implement any of NAND, NOR, or NOT. (There are a very few exceptions, like ECL, whose lack of gain makes them very intolerant of voltage variations)
So if you look at an AND gate - or an OR - you will find a NAND followed by an inverter - or a NOR + inverter.
That makes AND not only more expensive and power-hungry than NAND, but also slower.
The fact that any combinational boolean expression can be rendered into sum-of-product form (AND then OR), and trivially transformed into NAND-NAND form simply by inverting all the intermediate signals (using DeMorgan to implement the OR function with NAND gates) makes a network of NAND gates incredibly attractive way of implementing it. (Ditto Product-of-Sums, using only NOR gates).
simulate this circuit – Schematic created using CircuitLab
This shows how AND and OR gates can be implemented using either NAND or NOR technologies (Exhibits A and B).
It also shows how a simple expression in SOP form
(A AND B) OR C would be implemented if you simply used AND and OR gates formed from NAND blocks.
Hopefully it's obvious that all you need to do is delete pairs of inverters to arrive at the final NAND circuit.
The result uses only 2 levels of gain instead of 4 if you used AND/OR, so for the price of a little extra thought, your logic is twice as fast.