Looking at the data sheet, it would appear one should be able to use N chips to 'cleanly' drive N displays with N+4 pins and no other logic. Tie D0-D3 of all the chips together, and use a separate pin for each latch-enable input.
If one didn't mind having one of the displays show an arbitrary garbage value briefly when loading the other, one could save a pin by eliminating the latch-enable input for one of the displays.
Personally, my inclination would be not to bother with the 4511 at all; just use one 74HC595 for each display, tie the shift-clock of all chips to one I/O pin, tie the load-clock of all chips to one pin, and tie the data input of one chip to a third I/O pin. The the data input of each remaining chip to a shift output from a preceding chip (the data output of the last chip is unused).
Using that approach, three I/O pins can drive an arbitrary number of displays; unlike the 4511, the 74HC595 wouldn't limit you to displaying digits. If you want to save an I/o pin at the expense of a chip (or at least part of one), rig a two-bit counter with a count signal on the first 74HC595's shift-data pin, an async reset on the 74HC595's clock wire, and bit 1 of the output (indicating two pulses since reset) to the 74HC595's load-clock. If the counter advances on rising edges, and has an active low reset, one would shift out all the data "normally", but leave the clock high after the last bit and drive the data line low-high-low-high.