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Below is a block diagram that shows an op-amp in negative feedback with feedback network made from resistive divider:

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The encircled block is Op-Amp with 1 and 2 as its inverting and non-inverting pin respectively. I am assuming ideal conditions.

This would always be a stable system unless there is a delay in the feedback path. If we give a step input to the system and if the delay of the system is small then there would be no overshoot above the input step voltage but as we go on increasing the delay the system would start to overshoot and for higher delay it can become unstable. Below are the diagrams that show the system with delay and its response to the step input:

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For this system with ideal delay, I read that if the delay \$T_d\$ is greater than \$\dfrac{\pi}{2} \cdot \dfrac{k}{\text{unity gain freq}}\$, the unity gain frequency is the \$\omega_u\$ in the diagram above, than the system would become unstable and its output would start diverging.

For the second order system the block diagram is shown below, here the delay element is first order, let's say it is some RC delay: enter image description here

The delay element has a single pole at \$p_2\$. I read that this system is unconditionally stable with delay being \$1/p_2\$. From the above requirement of the delay, we can state that unconditional stability means the delay \$T_d\$ for this system always remains less than the above limit which is \$\dfrac{\pi}{2} \cdot \dfrac{k}{\text{unity gain freq}}\$.

Since the delay is of the order of \$R \cdot C\$ of the delay element and the \$R \cdot C\$ value can be made arbitrarily large, I think it is not always guaranteed that the delay will be restricted within this limit and hence system should go towards instability whenever the delay exceeds this limit.

Could someone please explain this apparent paradox about why the system is unconditionally stable even when the delay could be greater than \$\dfrac{\pi}{2} \cdot \dfrac{k}{\text{unity gain freq}}\$.

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    \$\begingroup\$ Are you confusing 'delay' and 'lag'? 1/p2 is a lag, Td is a delay. It's impossible for a 1st or 2nd order system, comprising lag terms and integrators and with no negative or zero coefficients, to be unstable. But a delay introduces a phase angle of \$-\omega T_d \$ with unity gain at all frequencies, therefore it can give rise to an unstable closed-loop if the open-loop phase margin goes negative. \$\endgroup\$ – Chu Dec 1 '15 at 23:48
  • \$\begingroup\$ @Chu....Thanks for this helpful comment...but could you please explain what do you mean by lag. Because the delay Td is the shift of the signal in time domain i.e. f(t) -> f(t-Td). And for the RC-delay case it is of the order of R*C. \$\endgroup\$ – sarthak Dec 2 '15 at 16:38
  • \$\begingroup\$ @Chu....Could you please prove that the delay of the RC system is less than or equal to (pi/2)*k/unity gain freq. \$\endgroup\$ – sarthak Dec 2 '15 at 17:24
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In your second example (2nd-order system with feedback) the phase of the loop gain function will approach the critical value of -180 deg for infinite frequencies only. Tha means: The phase shift will never reach -180deg at a fixed frequency - and the systenm will be stable.

In your first example (first order with fixed delay block) the loop gain phase will not be limited to any fixed value. Instead, the phase will rise with the frequency without any limitation. Hence, if the loop gain is larger (smaller) than 0 dB at a total phase of -180 deg, the closed loop system will be unstable (stable).

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  • \$\begingroup\$ Thanks LvW...that's true....but I was thinking in terms of delay of the loop during the transient response, Td in my question above. As I mentioned in the question, for delay greater than (pi/2)*(k/unity_gain_freq), the system should become unstable. Since the delay of the second example is of the order of 1/p2, by choosing p2 sufficiently small I can make the delay greater than the above limit. Could you explain in terms of this delay why system is still stable, even after exceeding the maximum delay limit. \$\endgroup\$ – sarthak Dec 1 '15 at 18:09
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    \$\begingroup\$ The question of stability of such a system must be answered with regard to the stability criterion in the frequency domain - because the answer depends on the gain and phase shift within the loop. It is not sufficient to look at the phase shift (or delay) only - at the same time you must also look onto the gain of the loop (and this again is the frequency domain). \$\endgroup\$ – LvW Dec 1 '15 at 18:31
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\Consider the open-loop with gain, \$\small K\$, integrator \$\frac{1}{s}\$, and delay \$\small e^{-sT}\$.

Phase angle (in radians) is: \$\small \phi=-\frac{\pi}{2}-\omega T\$, and gain is \$\frac{K}{\omega}\$.

For unity loop gain, \$\small K=\omega\$, which means, at this frequency \$\small \phi=-\frac{\pi}{2}-K T\$, and for a phase angle of \$-\pi\$, which would give a conditionally stable system (i.e. oscillatory):

\$\small -\pi=-\frac{\pi}{2}-K T\$ or \$\small T=\frac{\pi}{2K}\$, and including the feedback resistor network with gain, \$\frac{1}{k}\$, we have the condition: \$\small T=\frac{k\pi}{2K}\$

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  • \$\begingroup\$ @Chu...Thanks for the proof.....But I have one last question....Why does "lag" not cause instability? For the step input if there is a huge lag between the output voltage and the sensed voltage (the voltage that is being subtracted from the input in the feedback diagram), the loop is going to increase the output voltage beyond the input step and there would be huge overshoot....shouldn't this drive the system towards instablity? \$\endgroup\$ – sarthak Dec 3 '15 at 9:32
  • \$\begingroup\$ The maximum magnitude phase angle contribution for a lag is -90deg; combining this with the -90deg from the integrator gives a maximum magnitude phase lag of -180deg. So the open loop Bode plot phase never crosses the -180 threshold, hence never unstable. \$\endgroup\$ – Chu Dec 3 '15 at 10:06
  • \$\begingroup\$ @Chu....You said there is a difference between 'lag' and 'delay'...According to you -90deg is the delay, if I got you correctly. What I am talking abut here is the 1/p2 lag. This is the time the system takes to reach the steady state. If this lag is too large then the sensed voltage will be low even though the output of the loop is rising. This should cause a large overshoot when the output is beginning to rise with the step. Shouldn't this cause the system to become unstable. \$\endgroup\$ – sarthak Dec 3 '15 at 10:19

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