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I'm working in a mixed (analog and digital) PCB layout where I need to route some tracks from digital to analog ground area. They are general I/Os signals to control MOSFETs and clocks/data signals (around dozens MHz). The board is dual layer and I used this Texas article as reference: http://www.ti.com/lit/ml/sloa089/sloa089.pdf

The grounds are arranged as following image, red is digital ground plane and blue is the analog one. The grounds are connected each other at a single point (although not represented in the image) close to the plug of the power adapter, in top of the board. The issue is about the better way to trace those signals to analog circuit. I've read that digital signals should not come into analog ground, seen that is not possible in this case, my idea is to bring the tracks from digital into analog planes by two gaps (purple rectangles in the image), the central one would have the clocks/data signals and the right one would have the I/Os. The gaps positions are somehow related to components placement where signals will be connected to.

enter image description here

As you can suppose the analog circuit is sensitive and the aim is to find out a good solution to prevent noise and interferences coming from digital signal or its return. Is the proposed solution a good way?


[EDIT: 2015/12/02]

The analog part contains a CODEC which is connected to CPU.

I already have a prototype board which was designed following the arrangement showed in the image (except by the purple areas). This prototype is suffering interference from digital circuit, is possible to see some spikes in the FFT analysis. The spikes only happen when CODEC is working.

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    \$\begingroup\$ Don't split the ground plane. I don't care what documents you find from TI, AD, whoever saying otherwise. If you have to ask this question, the odds of it hurting more than helping are very high. \$\endgroup\$ – Matt Young Dec 2 '15 at 1:18
  • \$\begingroup\$ I agree with Matt. What is your analog stuff? Maybe there is no need for all this fuss. \$\endgroup\$ – mkeith Dec 2 '15 at 1:26
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    \$\begingroup\$ Correct component placement (following the "rooms" in your picture) prevents mixing the ground return currents, even with a continuous groundplane. If during prototype evaluation you see evidence of ground-coupled noise, you can try carefully cutting a slot into the plane, but single groundplane is simpler to manage, usually works well enough, and avoids problems of unwanted level shifting. For a 2-layer board, it will be very difficult to achieve a good reliable ground return system without a continuous groundplane. \$\endgroup\$ – MarkU Dec 2 '15 at 1:28
  • \$\begingroup\$ Matt is correct, it is much easier to design a circuit without split ground planes. However, maintain the "regions" -- keep analog components in your blue area and digital components in the red area. Try to place components with mixed signals on the "border" between the regions. \$\endgroup\$ – Pål-Kristian Engstad Dec 2 '15 at 3:18
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    \$\begingroup\$ If you go with a split ground you want to make sure that there is ground underneath the signal lines connecting the D and A pieces. As MarkU said.. think about the ground return currents... you want those to be underneath the signal lines. \$\endgroup\$ – George Herold Dec 2 '15 at 19:51
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Some basic stuff

Do NOT split the ground plane

If you've read the comments you'll understand that none of the engineers here (myself strongly included) think that you should split the ground plane. In your application it will hurt more than help (most most most likely). The way to intuit about planes is to recall that the thing that matters the most is the circuits' loop area.

The loop area is the enclosed region between the outbound and return circuit traces in 3D space. When you split the ground plane you will create some paths that look like this:

enter image description here

The outbound path goes direct, but the return has to take a much longer (and distant) route resulting in a large loop area. This makes it radiate (and receive radiation) much more efficiently (not desired).

The other issue in play here is that current follows the path of least impedance (NOT resistance). The high frequency elements of the current will follow (as best as possible) the outbound path, but the low frequency elements will follow the shortest path. This variation means that even if the loop area is low for some band of the energy, it may not be for others:

enter image description here

A solid ground plane, with good component placement, will give you the best of both worlds.

Increase your decoupling at the digital IC's power pins

This is the best layout:

enter image description here

...and these parts should be placed immediately adjacent to the Digital IC's power pins. Ideally:

multiple vias to power plane/track --> Capacitor's positive pour area --> IC pin.

enter image description here

Make the board thinner

Remember the all-important loop-area? It bites you again with a 2-layer board. In a 2-layer board, the full-thickness of the PCB is the separation between outbound and return current paths. If you make the board 1/2 the thickness, you will 1/2 the loop-area without changing your layout at all! With a 4-layer board at standard 1/2 thickness (0.8mm) the path separation will be around 0.26mm (e.g. 1/3 of a 2-layer board of the same overall thickness). That means a 4-layer board would be 3 times better at reducing cross-talk and unintended radiation (first order approx).

enter image description here

Maybe not possible?

Look, you might just be asking too much...

  • 24-bit ADC is extremely sensitive
  • 1GHz switching in a digital IC is very fast
  • 2-layer board implies broken planes and wide plane-to-plane separation
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    \$\begingroup\$ My most recent 24-bit ADC evaluation board has 8 layers... \$\endgroup\$ – MarkU Dec 2 '15 at 21:15
  • \$\begingroup\$ @DrFriedParts in the case of 4 layers, bottom and top layers wouldn't have copper area connected to GND? \$\endgroup\$ – Ricardo Crudo Dec 8 '15 at 19:07
  • \$\begingroup\$ @Ricardo -- They (top/bottom layers) could have copper pours that are ground-tied, but the effect of that is significantly less important than the plane underneath in most situations. The pours will be isolated from the ground plane by a much higher impedance than the plane itself and the parallel surface area between two features on the same layer is only about thickness and length, rather than width and length for two features on different layers. \$\endgroup\$ – DrFriedParts Jan 3 '16 at 7:41

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