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In the below figure, the the inputs are a,b,c and d and the outputs are Zo and Z1.There is a loop in the circuit.

How can i tell if the circuit is combinational or sequential?

enter image description here

edit: The outputs of interest here are z1 and z2 which are given by:

z1 = (a.b'.d) + (c.b.d) + (b.c.d)

z2 = c + a.b'd .

I have the outputs depending on inputs but can i conclude that it's a combinational ckt ? Is there any concept i am missing to understand?

at the extreme left is the inputs a,b and c in order.The output of 1st level OR gate is z0 and "d" is the input to the 4th level AND in centre. The output of the same AND gate is taken as z1. The 5 th level lower AND gate has inputs "b and c".

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  • \$\begingroup\$ I'm a bit rusty on this [hence a comment not a firm answer], but this looks to me like an asynchronous sequential circuit. \$\endgroup\$ – Fizz Dec 2 '15 at 6:43
  • \$\begingroup\$ just by looking at it? can you somehow give some reasoning to prove its sequential \$\endgroup\$ – Ashik Anuvar Dec 2 '15 at 6:44
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    \$\begingroup\$ Please add a non-blurry picture of the schematic. Otherwise I have no idea what letters are there. \$\endgroup\$ – Fizz Dec 2 '15 at 7:23
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If you have combinatorial circuit with a feedback path from output to input then it's [by definition] an asynchronous sequential circuit. https://books.google.com/books?id=1QZEawDm9uAC&pg=PA176

You have to make sure there's real state preserved there, i.e. the state saved actually affects the output(s). Otherwise it's a bogus/inconsequential "sequential" circuit, so really just combinatorial. In real life nobody would design that, but this being an academic exercise... you need to check.

You need to write (and simplify) the expression for z2 [if that's what I've circled below is called] and see if it actually depends on the old value of any inputs or not. Rafiquzzaman's textbook (to which I've linked) shows how to do this on an example (which actually has two state bits, but fewer inputs). Basically you treat old and new values as different variables (in this case z2) and apply k-maps etc. to simplify the expression to obtain a transition table for z2.

enter image description here

Regarding your equations, they seem wrong because there's no dependency of any on any [prior value of z]. Unless you've already simplified them... in which case, why are you still asking this question? But then your image so blurry I can't read practically any letters in it.

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  • \$\begingroup\$ check out the edit \$\endgroup\$ – Ashik Anuvar Dec 2 '15 at 7:15
  • \$\begingroup\$ ok at the extreme left is the inputs a,b and c in order.The output of 1st level OR gate is z0 and "d" is the input to the 4th level AND in centre. The output of the same AND gate is taken as z1. The 5 th level lower AND gate has inputs "b and c". \$\endgroup\$ – Ashik Anuvar Dec 2 '15 at 8:35
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Sequential logic implies that previous inputs effect current outputs, which given the feedback you have in the circuit you do have. On the other hand when most people (including me) think of sequential logic they picture logic that is registered with state and clocked (e.g. you have flip flops). What you have here is sequential logic, but it's asynchronous (you don't have a clock input). At first glance I would have wrongly called this combinational since I just looked for a register/flip flop somewhere, but because you have feedback your output depends on both current inputs and previous inputs.

To see this assume for a second that a=1, b=0, d=1, c=x. This means that your feedback path (the second input to the or gate with c as input) is driven high. Z0 is now 1. Assume now that you toggle a low. Z0 will still be high. That means that Z0 is dependent both on current inputs as well as previous inputs. Now for fun set d=0. Now you've cleared Z0.

From wikipedia: "In digital circuit theory, sequential logic is a type of logic circuit whose output depends not only on the present value of its input signals but on the sequence of past inputs, the input history.1[2][3][4] This is in contrast to combinational logic, whose output is a function of only the present input. That is, sequential logic has state (memory) while combinational logic does not. Or, in other words, sequential logic is combinational logic with memory."

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  • \$\begingroup\$ even latches are sequential ,but they don't have clock inputs.If the output is going to depend on its previous values then it sure is sequential right? \$\endgroup\$ – Ashik Anuvar Dec 2 '15 at 6:33
  • \$\begingroup\$ @dexter_6174 yeah that's true. \$\endgroup\$ – Doov Dec 2 '15 at 6:41
  • \$\begingroup\$ ok,but can try to prove that its not sequential \$\endgroup\$ – Ashik Anuvar Dec 2 '15 at 6:43
  • \$\begingroup\$ If the output was entirely dependent only on the inputs then it would not be sequential. But in this case your output effects the "next" output (after propagation delays etc) so it's sequential. \$\endgroup\$ – Doov Dec 2 '15 at 6:48
  • \$\begingroup\$ It's hard to make out the fuzzy text in the diagram, but you just need to make sure that the output is actually effected by the state. If it is then it's sequential. If it's not then it's probably just a pedantic homework question. \$\endgroup\$ – Doov Dec 2 '15 at 6:55
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Does it store state?

If there exists a coding for the inputs, for which the internal nodes can be in a choice of states, then it's sequential.

For instance a cross-coupled pair of NAND gates, the classic SR latch, is sequential, because an input of (11) does not define the state of the gate outputs, they can be (01) or (10) depending on the history of the inputs.

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To be honest, this is a combinational feedback and combinational feedback is a SIN. You should never use an output which you produced as an input to yourself without registering it. I'm sure this was given to you as an exercise, but these kinds of circuits are never used in the industry as the output has a very good chance of going into a forever changing loop and will never settle down.

You should always use a flipflop to register the output first. When the clockedge arrives, the output is used to do the new computation and it will be ready at the input of that flipflop before(a setup time) the next clock edge.

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