I have been using the Analog Devices AD9553 Eval Board, I am operating it as a clock translator, inserting a 10MHz LVDS differential signal and setting the device to produce a 100MHz LVPECL differential signal. I aim to operate the device in the LBW region (B=0.17KHz) as my signal is not expected to deviate in frequency by drastic amounts.
At first I had issues with phase locking all together, but this was remedied (so may it seem). I can observe the lock signal remain high for the majority of the time, dropping low rarely.
However my main concern is that my system is supposedly locked - my 100MHz LVPECL signal does not stay stationary on the oscilloscope when triggered from the sinusoidal 10MHz reference signal. I am observing the sinusoidal reference signal as I cannot probe the LVDS signals when connected to the PLL (my scope only has 1M and 50R termination modes and this interferes - Scope:TDS5104B). I know there is not a problem with the LVDS conversion stage as all those signals are stationary on the scope.
I have had a play around with the values in the registers but to no avail (N Div etc). I have attempted to use the debug mode to view the PFD signals etc from the LOCK pin but they show nothing on the scope, the only one I can observe is the XTAL clock. I take it that because there are no signals on the PFD div 2, PFD ref div 2 and the PLL feedback div 2 - that there is a problem with my reference signal, values or the device.
Regarding my setup, I am prototyping the system on breadboard, I do not know if this could be a cause of problems (I have kept the wire lengths as small as possible and have a COAX going from the breadboard to the EVAL board) , but I am confused as it says the PLL is locked - but is infact not locked to its reference source. Attached is one of the combinations I tried from the EVAL board wizard software. AD9553 Datasheet: http://www.analog.com/media/en/technical-documentation/data-sheets/AD9553.pdf
Guidance & Advice would be very much appreciated.
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