I'm trying to implement a simple latch on a ZedBoard via Vivado.
begin process(D,Enable) begin if(Enable = '1') then Q <= D; Qbar <= not(D); end if; end process;
I'm using user I/O on the constraints for the inputs/outputs. I assign the inpus to two SWITCH Pins and the outputs to two LED pins.
The routing (implementation phase) gives me the following error:
[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule. < set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Enable_IBUF] >
Enable_IBUF_inst (IBUF.O) is locked to IOB_X1Y125 and Enable_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y31`
The two suggested solutions to the problem are here and setting the
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Enable_IBUF] > works but I would like to understand solution 1
1) Move the clock input to a clock capable pin. since it seems important.
How can I find a clock capable input that I can press/move like I do on the switch?
Edit: Link of the ZedBoard pins (already tried C19 -> FMC_CLK1)