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So, for a project, I had to design a 4bit SRAM circuit with 4 inputs and an output. There's an enable, write, and 2 address pins, and an output read pin.

For the most part, I got the entire circuit working. I was able to get the individual SRAM circuits working, and also get them working when hooking up directly a 2bit in 4 output decoder for selecting each cell. The problem comes when I want to add the enable switch (during testing, I bypassed the enable switch by just using the address output as enable). Any suggestions on how to get around this? I'd post a schematic but I only have drawings and I'd have to completely redraw them to look nice anyways.

EDIT: rough schematic photo

The way we are supposed to do this is using an n-channel MOSFET hooking the address decoder output to the gate, the enable to siurce, and the drain connects to a small dual AND gate to pass both write and not(write) to the SRAM cell.

Enable works fine enabling the the write, but there comes a problem when I want to write to different cells. The circuit basically acts unpredictably - I do a write operation to a second cell and the first cell get written to as well, but if I do the first cell alone it works fine. Sometimes it doesn't write to 2 of them sometimes it works fine but most of the time now. And I've noticed when probing around the when I probe the gates of, say, the first SRAM enable MOSFET, it'll suddenly turn off that cell if it wasn't supposed to be on.

A somewhat solution I found was putting a resistor from the drain MOSFET to ground but then I ran into the problem that I don't have a high enough value resistor to pull the voltage high enough to write to the cell. I guess I've boiled it down to come weird parasitic voltage on the MOSFET but for the life of me can't figure out how to fix that.

Also, as a note, the class is requiring me to use a CD4007 for the FETs, I've actually tried with BJT's and the circuit works fine that way but we aren't allowed to use those....

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Combining the write enable with the address decoding is simply another AND operation. You can either add another pair of gates or simply use 3-input gates where you currently have 2-input gates driving the SRAM cell. Using a single pass transistor where you have shown it doesn't make much sense.

In a real SRAM, pass transistors are used to connect the SRAM cell to the bit lines, which are used for both reading and writing. The gates of the pass transistors are connected to a "word line" that selects all of the bits of a given word all at once.

The bit lines are connected to both drivers (for writing) and sense amplifiers (for reading). The write enable is used to enable the bit-line drivers.

schematic

simulate this circuit – Schematic created using CircuitLab

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    \$\begingroup\$ You know, I'm not exactly sure why I was doing it this way either. I think maybe I got mixed up because for one cell, we have to build it at transistor level (like the schematic you show) and that has the pass transistors. I can't believe I sat here doing truth tables forever trying to figure out a way to not do a pass transistor not realizing I just needed an AND gate... \$\endgroup\$ – Anthony Albanese Dec 3 '15 at 14:05
  • \$\begingroup\$ Also thank you for pointing that out. Now everything works I just have to figure out how to get a "read" signal while address (and further, the "word" line) is high but enable is low. \$\endgroup\$ – Anthony Albanese Dec 3 '15 at 14:22

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