I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis.

In particular I noticed that there is a section in the .tsi file called "Constraint interaction for Unconstrained path analysis" under which I have something like

"X paths removed by TS_my_derived_clock_constraint",

where X is a very big number and coincide with the number of analysed paths reported in the Static Timing report under the section Derived Constraint Report.

How should I interpret this information? Are these paths analysed or not? Is it normal that the very same number appears in these two files? What does it mean "interaction for unconstrained paths"?

The timing constraint I use is something like:


This is a differential clock entering in a Xilinx clock generator, from which the derived clock constraint is obtained.

The Translate report issued some warnings but they are about mysterious "logical net 'NX' has no driver", with X are all numbers from 85 to 165 and some warnings about TNM "bus_name_reset_resync" that does not drive any flip flops. They seem ok to me.


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  • \$\begingroup\$ Maybe you have two overlapping constraints. Does the "Translate" step reports any warnings? Could you please add your (relevant) timing constraints to your question? \$\endgroup\$ – Martin Zabel Dec 1 '15 at 20:20
  • \$\begingroup\$ @MartinZabel there are some overlapping constraints in the design, mainly due to DDR and Ethernet usage, but they are reported in their sections in the .tsi file and the paths removed from the analysis because of these constraints are very limited in number, so I suppose they are correct (moreover, these constraints come directly from ISE, I didn't add them to my .ucf) \$\endgroup\$ – Alessandro Dec 1 '15 at 20:41
  • \$\begingroup\$ Just a note: the constraints for IP cores are stored in a .ncf file beside the .ngc of the IP core. \$\endgroup\$ – Martin Zabel Dec 3 '15 at 19:50

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