I'm using Xilinx ISE 14.7 to implement my design but I have some doubts about how to read the constraint interaction report (.tsi) generated during the Post Place&Route Static Timing Analysis.
In particular I noticed that there is a section in the .tsi file called "Constraint interaction for Unconstrained path analysis" under which I have something like
"X paths removed by TS_my_derived_clock_constraint",
where X is a very big number and coincide with the number of analysed paths reported in the Static Timing report under the section Derived Constraint Report.
How should I interpret this information? Are these paths analysed or not? Is it normal that the very same number appears in these two files? What does it mean "interaction for unconstrained paths"?
The timing constraint I use is something like:
NET "CLK_P" TNM_NET = CLK_P; TIMESPEC TS_CLK_P = PERIOD "CLK_P" 200 Mhz HIGH 50%;
This is a differential clock entering in a Xilinx clock generator, from which the derived clock constraint is obtained.
The Translate report issued some warnings but they are about mysterious "logical net 'NX' has no driver", with X are all numbers from 85 to 165 and some warnings about TNM "bus_name_reset_resync" that does not drive any flip flops. They seem ok to me.