Hi Am trying to understand what am doing wrong, I connected CE to CC with a small Rload am designing it so Zout of the second stage equal Rload to get Maximum output.

From what i read in CC-amp Zout = RE||(r'e+ ((R1||R2||RS)/Bac)) were RS is the source resistance, i figured since CC-amp is connected to CE-amp then RC takes place of RS.

I reedited the calculation and obviously it came out wrong.

Bac = 100
Rload = 30
RS= RC = 1800
(R3 || R4 || RS) / Bac = 18 since RS << R3||R4
r'e + 18 = 30 => r'e = 12
IE = 25mV /r'e = 2.08mA
RE = 100*Rload = 3000
VE = 6.24V

Zout = RE||(r'e+ ((R3||R4||RS)/Bac)) = 29.7
Zout = Rload

Recalculate DC for final result

Vth = VE +VBE + Delta= 7.2V
Rth = Bdc(Vth - VBE / IE - RE) = 12500
R3 = Rth * (VCC / Vth ) = 15625
R4 =1/ (1/Rth - 1/R3) = 62500

Tried different ways but nothing, is the cutoff caused by first stage i tried to keep Q1 in midpoint and without CC it Amplifies signal without distortion, is it a cap problem or is it cause the current is to high

thank you for the help enter image description here

  • \$\begingroup\$ What are you actually trying to do? I don't see a question here. If you make a CC output amplifier, it should be very low output impedance, not to match the load. If you want an output load matching amp, it should be from a series/parallel feedback stage where the output impedance can be designed \$\endgroup\$ – Neil_UK Dec 4 '15 at 7:39
  • \$\begingroup\$ A CC has a a voltage gain of one and low output impedance and high input impedance so connected it to a CE so it should not overload CE but it did by lowering AV of first stage and the signal is distorted when connected to a small load. Am trying to Amplify in CE and use CC to match its Zout with Rload. Also my calculation was it correct to assume RC of the CE replaces RS and why is the signal distorted. Am trying to understand Transistors \$\endgroup\$ – ramon22 Dec 4 '15 at 10:37
  • \$\begingroup\$ Reduce RE2 .... \$\endgroup\$ – user_1818839 Dec 4 '15 at 11:17
  • \$\begingroup\$ When the transistor is conducting, your output impedance is as you calcuated, for the -ve half cycle, the TR turns off, and you're left with RE2 as the output impedance \$\endgroup\$ – Neil_UK Dec 4 '15 at 20:43

Let's say the base of Q2 is biased to an average voltage of Vbias. Ideally, C3 would be charged to an average voltage of Vbias minus Vbe_of_Q2.

When the signal going to the base of Q2 is in the positive phase, it would be higher than Vbias, Q2 turns on. The output impedance is similar to your calculation, being the combination of the output impedance of Q2 and RE2.

But when the signal goes into the negative phase, it would be lower than Vbias. Given the voltage charged across C3, current flows backward, and Q2 turns off. Now the output impedance is simply RE2. RE2 cannot drive Rload because it is 100 times of Rload. Therefore the lower part of the sine wave signal is lost at Rload.

It is actually worse than the description above because C3 would be charged to an average voltage higher than Vbias minus Vbe because of the imbalance. So I actually cannot explain why the yellow trace only lost about half of the sine wave and not more.

  • \$\begingroup\$ I made the coupling caps large so they will not have much effect on circuit since in AC they will act as shorts and Q2 is biased by the second voltage divider and will provide the necessary voltage to overcome VBE. When i increase the Rload by 10X the distortion stops, am not sure its possible to achieve max power transfer in CE&CC without a transformer cause IEQ2 and VECQ2 will not be in midpoint that's why i think am getting the cutoff. \$\endgroup\$ – ramon22 Dec 4 '15 at 14:13
  • \$\begingroup\$ No matter how large C3 is, it will never be a short to DC, therefore the average DC voltage would still be there across C3. Why not add probes at the emitter and the base of Q3, in additional to the one at Rload, to compare the voltages at the 3 points. \$\endgroup\$ – rioraxe Dec 4 '15 at 18:48
  • 2
    \$\begingroup\$ This is about a common misconception, a different topic than above, about max power transfer. When you are stuck with a particular output impedance, then picking the load impedance to be the same as output impedance gives max power transfer. When you are free to modify the output impedance, then max power transfer is always when output impedance is zero (or as low as possible) regardless of the load impedance. \$\endgroup\$ – rioraxe Dec 4 '15 at 18:51
  • \$\begingroup\$ You just blow my mind with the max power transfer thank you i would never have thought of that, i will try it out and see what will happen \$\endgroup\$ – ramon22 Dec 4 '15 at 19:16

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