Delay and Stablity in Negative Feedback Systems: Confusion-2

Question

This question is in reference to my earlier question:
Delay and Stablity in Negative Feedback Systems: Confusion

In that question I wanted to ask why the second order system is always stable. But I could not understand the issue well from the answers. So I am asking in a more definite way what doubt I have.
Delay block is ideal
When a step input is applied to the system with, say, ideal delay, the output would began to rise and after the specified delay Td (which is delay of the 'delay' block shown below in the figure) the sensed input would began to rise with the output. This is shown in the figure below, where the red curve shows the output, the blue curve is the sensed voltage which would be subtracted from the input (here the delay Td is shown to be 5s) and the black dotted line represents input step (Although, the figure is shown for speed but similar analogy can be drawn for voltages as well). Clearly, if this delay is too large then the error voltage (which is the difference between the input and the sensed voltage and is the input to the integrator) would remain high and the output of the integrator would continue to rise resulting in large overshoot. This should cause instability in the system. Is this correct? Delay Block is RC system
If this delay block is a first-order RC system (so the overall system is second order now) and if the product R*C is very large, again the blue curve would rise very slowly causing the error to remain large and the red curve, which is the output of the integrator, would again have a large overshoot above the input step. Shouldn't this again cause the system to become unstable?
In other words, for large product of R*C there should be large overshoot. But is the system still stable? If so, why?

Answer 1

Using your system as an example, it's interesting to consider what happens during the first 10sec, or so, following the application of a unit step at the system input (this may convince you that it's far easier to base a stability analysis on the open-loop!)

\$\small 0<t<5\$: The output from the delay is zero; the error signal is unity, hence the system output is a unit ramp (integral of step = ramp). Hence, the output reaches 5 at t=5.

\$\small t=5\$: the unit ramp begins to emerge from the delay

\$\small 5<t<6\$: The unit ramp subtracts from the unit step, hence the error signal ramps down from 1 and reaches zero at t=6. As the integrator input is now ramping downwards, the integrator output is no longer a ramp, it's a parabola, gradually diverging from the original ramp (integral of a ramp is a parabola). The integrator output reaches 5.5 at t=6.

\$\small 6<t<10\$: The error signal is now negative, and is still a negative-going ramp with a gradient of -1. The integrator output decreases parabolically from 5.5, reaching -2.5 at t=10.

\$\small t>10\$: The parabolic sections of the integrator output now begin to emerge from the delay and subtract from the unit step input. Note that, when the delay output signal goes negative, the error signal will be >1 and the integrator output signal will exceed the earlier ramp in magnitude. The system is unstable.

Choosing a smaller delay time (or applying a fractional integrator gain) will render the system stable (try it, if you've got the odd day to spare!)

In contrast, if the delay is replaced by a 1st order lag, the feedback path is far less aggressive. The output from the lag starts to grow exponentially from t=0 and begins to reduce the error signal immediately. This means that the error signal falls exponentially, from t=0, and the system output grows in a much more leisurely fashion. The worst case is where the lag is replaced by an integrator, giving rise to a 2nd order system with zero damping and an oscillatory response. This is critical stability, and things can't get any worse from a stability perspective. Therefore the 2nd order system with poles in the LH s-plane cannot be unstable. In terms of electrical components, it's an LC circuit without any R.

Answer 2

sarthak, regarding the first question, my answer is: Yes - in principle, your description is correct. One can show that - as an example - for a unit integrator H(s)=1/s the stability limit is at a delay function of exp(-s*1.57). For larger (smaller) values of delay time T=Pi/2=1.57sec the circuit shows growing (decaying) amplitudes.

In case of an RC block with a very large time constant the error voltage at the beginning is pretty large (as you have mentioned) and the integrator output will rise (theoretically) to very high voltages. This is because there is a very small feedback effect only. Therefore, each real circuit will come to the limits set by the supply voltage. But this does not mean that an ideal circuit (without supply limits) would be unstable.

Because of the large time constant of the RC section the large error voltage is reduced very slowly (charging of the capacitor) and the resulting transient has a very large period. But the time shift between both signals never reaches the critical value that causes rising oscillation. When it comes closer and closer to this critical value the rising amount of feedback - at the same time - reduces the error voltage.

As a result - the circuit is always stable. As I have mentioned in my answer to your previous question, such stability analyses are easier to understand in the frequency domain.

Answer 3

An integrator output has a phase shift of 90 degress to any sine wave input. If that output is fed back to the input (via an RC), the criteria that determines oscillation is that there must be 180 degrees overall phase shift.

Quite simply, an RC network cannot produce that extra 90 degrees until the input frequency is infinite. This means that the circuit may overshoot but will not become unstable.