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Although I can understand the difference between programmed IO (PIO) and interrupt (INT) transfers, still there is something vague.

In PIO, the processor repeatedly checks READY pin to see if the device is ready. However, in interrupt mode, the processor checks the INT pin at the end of the instruction cycle.

My question is, in interrupt mode, the processor still has to repeatedly checks the INT pin. I know that in this mode, the external device send the interrupt signal, but how processor becomes aware of that interrupt? The processor has to repeatedly check the INT pin on every cycle (or instruction cycle). Doesn't it?

References:

{1} http://www.louiewong.com/archives/137

{2} https://www.quora.com/What-is-the-difference-between-programmed-driven-I-O-and-interrupt-driven-I-O-What-is-one-advantage-and-one-disadvantage-of-each

{3} http://homepage.cs.uiowa.edu/~ghosh/Chapter3.ppt

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In PIO mode the processor is executing instructions that check the IO. That means it's not executing other instructions during that time.

In IRQ mode the check is performed by the same part of the hardware that normally increments the instruction pointer, or handles jumps. The check itself doesn't "cost" anything other than a tiny bit of processor chip area.

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  • \$\begingroup\$ So, do you have any example for them? What I understood is that they both do the same thing but the latter has lower cost. That means, at the end of the day, CPU has to periodically check to see if device has something new for it, but in interrupt mode, the CPU only checks some status bits \$\endgroup\$ – mahmood Dec 4 '15 at 16:49
  • \$\begingroup\$ Instead of repeatedly executing software instructions to check the device, it repeatedly checks pins \$\endgroup\$ – mahmood Dec 4 '15 at 16:50
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    \$\begingroup\$ The interrupt recognition and calling of the Interrupt Service Routine is done entirely in hardware - the main program doesn't have to check any status bits for the interrupt to occur. \$\endgroup\$ – Peter Bennett Dec 4 '15 at 17:00
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The difference is that with PIO the CPU has to periodically execute instructions which read the READY pin and decide what to do about it, whereas in interrupt mode the CPU just keeps executing the main code and is 'interrupted' by extra hardware which is monitoring the INT pin.

Typically the hardware interrupt saves the current PC on the stack and then jams the interrupt vector address into it, causing the CPU to jump to the interrupt handler code. This may only take a few cycles, but since the main program is not aware that it has happened the interrupt handler must also save and restore any registers that it changes. As a result the time required to process an interrupt may be much longer than using PIO.

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  • \$\begingroup\$ So the concept is to check related IO pins via software codes (PIO) or hardware circuits (IRQ). Thanks. \$\endgroup\$ – mahmood Dec 4 '15 at 19:41
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It helps to look at a processor architecture. Look up Mips pipeline with hazards. It can get a little complex, but what is being pointed out is that the PC(program clock) of processors is in itself the pointer. When something like an interrupt happens, it goes to the hazard unit, which also acts as the interrupt vector table. This vector table takes care of all the mapping and controls a few pieces of the processor to stall, jump, branch (ISR things). In many cases, it says to do something in Kernal mode, or syscall as MIPS calls it. This means a software interrupt.

In the case of PIO, everytime you want to check a pin, you must process instructions to point to that pin, call a peripheral to do that, report back, and check the results with another instruction.

enter image description here

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