I am trying to convert highly parametrized VHDL code to verilog. This VHDL code uses good amount of packages and records and I couldn't find the substitute for those in verilog. Also I am just 3 days old in verilog.
Package and entity files in VHDL are as follows:
package control_package is type control_ca_out is record reset : std_logic; end record; type control_in is record clk : std_logic; ha : psl_control_in; dc : dma_dc_out; end record; type control_out is record ca : control_ca_out; ah : psl_control_out; cd : dma_cd_in; end record; entity control is port ( i : in control_in; o : out control_out ); end entity control;
Package and entity are in separate files. How do i implement the same in verilog? I know there's a way of packing all fields of records in single vector and then use part-select to access different fields of record. How could I include them in separate module in verilog?