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I am attempting to create a simple logic circuit simulator. I am having a hard time figuring out how does a logic gate behave with an input changing faster than its propagation delay.

When attempting to connect a high frequency clock to an invertor logic gate with a 1 second delay in a simulator, the output stayed the same for 1 second and then started following the pattern of the clock.

It seems as if the output was a following function: output(t) = NOT(input(t - delay)). Is this true? If so, why? Also, how would this work with different rise and fall delays?

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    \$\begingroup\$ It says "ouch" but gets on with it. \$\endgroup\$ – Andy aka Dec 5 '15 at 0:15
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It really depends on how the gate is constructed. For a completely accurate simulation, you have to do a transistor-level analog simulation. However, it is possible to extract timing parameters from a transistor-level simulation and abstract them out a bit. The output rise and fall times and propagation delays will depend on the input rise and fall times, output load capacitance, power supply voltage, temperature, and the state of the inputs. Yes, it is possible for the same input transitioning to have a propagation delay that depends on the state of the other inputs. These techniques are used in the timing models used in ASIC and FPGA design in both static timing analysis as well as timing-driven place and route.

Fundamentally, the propagation delay is determined by how long it takes for the output to transition in response to a change at the input. This depends on exactly how the gate is built at a transistor level. For a single two transistor CMOS inverter, the propagation delay is determined by the analog electrical characteristics of the transistors and their parasitic capacitance. The input will slew at some rate, then once the threshold is reached the output will start slewing. If the input changes before the output finishes slewing, then the output will start to slew back the other way and you will end up with a highly distorted output. So for a single inverter, the output for a change faster than the propagation delay would be an invalid logic level (i.e. x). However, "gates" can be far more complicated than a single inverter. For example, if you have a "gate" that is built from a string of 100,000 inverters, then the propagation delay of the whole unit will be 100,000 times the propagation delay of a single inverter and it is certainly possible to have multiple transitions 'in flight' at the same time, so long as these transitions are not faster than each individual inverter can handle.

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  • \$\begingroup\$ Is this simulation output wrong then or am I misunderstanding something? Circuit link (propagation delay on invertor 1s) and output graph (measured between NOT and BUF), clock frequency is 10Hz. Simulator link. Based on your answer I would expect the output to stay the same or be undefined. \$\endgroup\$ – David Porizek Dec 4 '15 at 23:03
  • \$\begingroup\$ Well, if the simulator implements the delay as literally just a delay and nothing more, then it is correct as per the implementation. However, whether this is a valid physical representation of what is going on depends on precisely how that gate would be implemented. \$\endgroup\$ – alex.forencich Dec 4 '15 at 23:09
  • \$\begingroup\$ Thanks for answering. If the gate was a two transistor CMOS inverter, would it be a valid physical representation then? \$\endgroup\$ – David Porizek Dec 4 '15 at 23:51
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    \$\begingroup\$ Let me pose a question instead: where would all of those transitions be stored during the propagation delay? \$\endgroup\$ – alex.forencich Dec 5 '15 at 1:32
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What you are describing is called "transport delay" in VHDL, as opposed to "inertial delay" in which events shorter than 1 second would silently disappear.

"Transport delay" is useful for modelling delay lines, very long cables, and so on, but "inertial delay" is a more accurate simulation of logic.

More information here

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The propagation delay is simply "the amount of time it takes for the head of the signal to travel from the sender to the receiver" (from here), it is not the bandwidth, which is how fast the system can respond to the input.
The output will behave as expected, but delayed by the propagation delay time.

With different rise and fall propagation delays it will be more complicated, because different part of the signal will be delayed differently, and the behaviour will not be so obvious.

Of course, all of this is valid for simple systems (i.e. the inverter), increasing the complexity will lead to incresed chance of unpredictable behaviour. (i.e. the race condition)

There are even circuits based on the propagation delay, i.e. the ring oscillator

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    \$\begingroup\$ Different rise and fall is possible. \$\endgroup\$ – pjc50 Dec 4 '15 at 20:42
  • \$\begingroup\$ Thanks for the information, could you provide an example? I have never encountered that. \$\endgroup\$ – FMarazzi Dec 4 '15 at 20:44
  • \$\begingroup\$ centers.njit.edu/ecelab/manuals/computer-engineering/ece-394/… "It should be noted that the transition period for the rising and falling edges of the same gate may not necessarily be the same, although it is normally desirable to have a symmetrical transition" \$\endgroup\$ – pjc50 Dec 4 '15 at 20:49
  • \$\begingroup\$ en.wikipedia.org/wiki/… \$\endgroup\$ – Fizz Dec 4 '15 at 20:54
  • \$\begingroup\$ Thanks. I have never thought about how rise and fall times modify the propagation delay value. \$\endgroup\$ – FMarazzi Dec 4 '15 at 20:56
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Roughly speaking there are two types of delay, "inertial" and "transport" (and combinations of both).

"inertial" delays represent capacitances (usually parasitic) that take time to charge and discharge. Most basic logic gates would fall into this category, as charging and discharging capacitances is the main cause of delay. Delays may not be symmetrical and may depend on the states of other inputs. If you look at the output on a scope you would see it ramp up/down to it's final level. If the input changes too often fast then it will never reach the levels it's supposed to reach and you will get an output that wanders up and down without actually reaching it's targets.

"transport" delays represent things that delay a signal without destorying it's shape. One example is a properly terminated transmission line. A long chain of gates can also look much like a transport delay for some switching rates as the individual gates have sufficient time to reach their target voltages but it takes some time for information to work it's way down the chain.

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