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I wrote clock generator module, i dont know if it is true but the problem is in my reg module. The error is:

ERROR:HDLCompilers:246 - "UpDownCounter.v" line 74 Reference to scalar reg 'clk_1Hz' is not a legal net lvalue

ERROR:HDLCompilers:102 - "UpDownCounter.v" line 74 Connection to output port 'clk_1Hz' must be a net lvalue

1 HZ CLOCK GENERATOR

module slowClock(clk, reset, clk_1Hz);
input clk, reset;
output clk_1Hz;

reg clk_1Hz = 1'b0;
reg [27:0] counter;

always@(posedge reset or posedge clk)
begin
    if (reset == 1'b1)
        begin
            clk_1Hz <= 0;
            counter <= 0;
        end
    else
        begin
            counter <= counter + 1;
            if ( counter == 25_000_000)
                begin
                    counter <= 0;
                    clk_1Hz <= ~clk_1Hz;
                end
        end
end
endmodule   

And here my Reg 4 bit module

module Reg4(I, Q, clk, reset);
input clk, reset;
input [3:0] I;
output [3:0] Q;
reg [3:0] Q;


reg clk_1Hz = 1'b0;
slowClock clock_generator(clk, reset, clk_1Hz);

always@(posedge clk_1Hz) begin      
    if (reset == 1)
        Q <= 4'b0000;   
    else
        Q <= I;

end
endmodule

Can u see my problem ? :(

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  • 1
    \$\begingroup\$ You got your answer, but in the future please add a comment telling us which line is the one with the error (line 74, in this case). \$\endgroup\$ – The Photon Dec 6 '15 at 1:25
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In the Reg4 module, change:

reg clk_1Hz = 1'b0;

to:

wire clk_1Hz;
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  • \$\begingroup\$ thanks. It worked but the warning is: CLK Net:value_reg/clock_generator/clk_1Hz may have excessive skew because \$\endgroup\$ – funky-nd Dec 6 '15 at 0:33
  • \$\begingroup\$ however, my project on basys-2 is working well despite warning \$\endgroup\$ – funky-nd Dec 6 '15 at 0:33
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    \$\begingroup\$ @cihangirND add a BUFG primitive between your 1Hz clock register and the output of the slowClock module. Otherwise the clock signal will be routed on normal routing networks and not the global clock network (which is what the excessive skew warning is about). \$\endgroup\$ – Tom Carpenter Dec 6 '15 at 2:02
  • \$\begingroup\$ @TomCarpenter wow thanks. 0 warning. did i placed it right ? i.hizliresim.com/82a3Ed.jpg \$\endgroup\$ – funky-nd Dec 6 '15 at 2:22
  • \$\begingroup\$ @cihangirND Indeed. I would have placed it inside the slowClock module for neatness, but when synthesised it will make no difference at all. \$\endgroup\$ – Tom Carpenter Dec 6 '15 at 2:24
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In the 1Hz code you haven't assigned any value to the clk_1hz. Hence no value will be assigned to it. Just include assign clk_1hz = counter[24]; outside the always block.

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