# How to specify timing constraint for two paths to have a equal delay in Vivado

I am trying to sample an asynchronous signal in multiple clock-domains. I do not care too much about the absolute delay from the source of the async signal to the sampling FF's, but I want to constrain each of the paths to have roughly equal delays. How would I do this in Vivado/.xdc?

• In the older tools, you'd put them in the same Timegrp and specify both a minimum and maximum delay. I expect there's a way to use the same approach in Vivado. But it's an unusual requirement, there's probably a better answer to the real problem. – Brian Drummond Dec 6 '15 at 15:58
• Indeed, it's an unusual application. I'm trying to implement a very fast deserialiser, using multiple phase shifted clocks. I want to measure the time of the rising edge of a pulse and hope to get down to a resolution close to the hold time of the FF's. I don't care for the absolute delay, I can calibrate for that. – burnpanck Dec 6 '15 at 17:39
• I guess one would ideally use the ISERDES for that job, but unfortunately I'm in a restricted environment, where this is unavailable (LabVIEW FPGA). – burnpanck Dec 6 '15 at 17:41
• how about set_data_check? this looks closer to what I'm looking for... – burnpanck Dec 15 '15 at 23:55