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According to my textbook, a CMOS must use both PMOS and NMOS transistors because a CMOS needs transistors that follow the positive logic system and transistors that don't follow the positive logic system. n-type enhancement mode MOSFETs do follow the positive logic system and n-type depletion mode MOSFETs don't follow the positive logic system, so why can't only NMOS transistors be used?

The positive logic system defines 0 (off) as low voltage and 1 (on) as high voltage.

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    \$\begingroup\$ Depletion mode FETs still "follow the positive logic convention" they just have an awkward requirement for negative gate voltages. \$\endgroup\$ – Brian Drummond Dec 6 '15 at 20:45
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    \$\begingroup\$ Possible duplicate of Why can't CMOS simply be made of n-type enhancement mode MOSFETs and n-type depletion mode MOSFETs? \$\endgroup\$ – helloworld922 Dec 6 '15 at 20:47
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    \$\begingroup\$ That's not what Wikipedia says. 0V is the more positive of the two interesting gate-source voltages. \$\endgroup\$ – Brian Drummond Dec 6 '15 at 21:07
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    \$\begingroup\$ @Travis: The point is whether "opened" or "closed" happens above the threshold voltage. Simply moving the threshold above or below zero doesn't change that. \$\endgroup\$ – Ben Voigt Dec 6 '15 at 21:08
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    \$\begingroup\$ For a depletion device, you still increase the gate-source voltage to turn it on, and decrease the gate-source voltage to turn it off. Changing the thresholds does not suddenly invert the polarity of the logic. \$\endgroup\$ – W5VO Dec 6 '15 at 21:09
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That's been done already. It's called "Depletion-load NMOS", as opposed to "CMOS" with the "C" meaning "complementary", i.e. both NMOSFETs and PMOSFETs.

The primary disadvantages of NMOS are(were):

  1. Its power dissipation is higher than CMOS since the pullups never turn off (versus PMOSFETs).
  2. Drive strength is asymmetrical due to high-side pullups versus low-side switches.
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A NMOS is on when the gate-source voltage is higher than the threshold voltage. For a depletion-mode NMOS, this threshold voltage is negative. Thus, if the gate-source voltage is zero, there is already a n-channel and some current may flow from drain to source. If the gate-source voltage is increased, then more current can flow. Thus, a depletion-mode NMOS still follows the positive logic convention.

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