I'm not particularly well acquainted with MOSFET logic design and need some verification on a few things to make sure I've got them correct, and to see if there's any better ways of doing it. I need to control a 12v battery input terminal with a 3V3 logic level from an ARM microcontroller. I've put the following circuit together while digging through some other answers on stack exchange.
Power_Control is the ARM GPIO and operates on 3V3 logic. Q1 is an N channel Mosfet with datasheet. It has V_GS(th) = 2.1, V_GS being either 0, when the GPIO is low and 3.3 when it is high. So I assume that should work, but I honestly don't know if that's how I'm meant to be reading the datasheet. According to my understanding, Enhancement mode NFET should be off when V_GS = 0 and on when V_GS>=V_GS(th) and a Enhancement PFET should be off when V_GS=0 and on when V_GS<=-V_GS(th).
Q2 is a P channel Mosfet with datasheet. It's got max V_GS of +-20V so I assume it's rated to handle my input and it has a V_GS = -3V and it should either be -12 when Q1 is allowed to conduct or 0 when it isn't allowed to conduct. Q2 datasheet doesn't specify it, but I'm assuming it's an enhancement mode. Is that a correct assumption to be making?
Practically speaking, will this circuit work for the desired outcome? Are there better ways to achieve it? Less components, cheaper price or if it would be possible to use 2 of the same channel FET's as it'll save on cost.