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Is it possible for an FPGA connected via PCIE to a CPU, to directly access peripherals (USB Ports, data, Ethernet, etc) connected to the same CPU via a chipset? I had an Intel based system in mind, with a x99 motherboard or something equivalent.

If it is possible how would the process be performed (Just rough steps.)?

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  • \$\begingroup\$ It depends. If the peripherals are PCIe based, and on the same root port as your device, then yes, if you know their bus-function-device address, and how to interface with them. \$\endgroup\$ – Tom Carpenter Dec 8 '15 at 23:32
  • \$\begingroup\$ I'm pretty sure that most peripherals on the motherboard are not on the same root complex - they connect to the chipset which connects to the CPU via (for X99 case) a DMI 2.0 bus. I'm doubtful that there is any way to directly route stuff from the PCIe device to the DMI bus. \$\endgroup\$ – Tom Carpenter Dec 8 '15 at 23:34
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The PCIe spec defines that devices can address each other, yes.

Whether that actually works is another question. Several chipsets have access control logic that requires the CPU to explicitly permit that two devices talk to each other.

This makes sense from a security point of view: if the sound card could instruct the graphics card to display a password prompt, you might type your password into the wrong window and send it across the network, and since no one expected the sound card to have meaningful attack surface, fewer permissions would be required to access it.

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  • \$\begingroup\$ So is that to say that if my FPGA contacts the CPU and requests to access a USB port the CPU would directly connect the two? \$\endgroup\$ – Gecko Dec 8 '15 at 23:41
  • \$\begingroup\$ The CPU needs to set this up proactively. You need to tell the PCIe root complex that this access is allowed, and the OS needs to ignore the USB controller from then on, because it is now under the control of the PCIe card. Obviously that is a mechanism that is only seldom used -- in fact I'd expect it to be mostly untested except for DMA transfers through the cl_amd_bus_addressable_memory OpenCL extension. \$\endgroup\$ – Simon Richter Dec 9 '15 at 1:50

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