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I am using ISE to write my first verilog code .

i wrote a counter :

`timescale 1ns / 1ps

module my_counter( input clk , output reg [3:0] out);

 always @(posedge clk) begin

 out <= out+1 ;

 end

 endmodule

then used ISE to make a testbench (added clk myself!) :

`timescale 1ns / 1ps

module mycounter_test;

// Inputs
reg clk;

// Outputs
wire [3:0] out;

// Instantiate the Unit Under Test (UUT)
my_counter uut (
    .clk(clk), 
    .out(out)
);

initial begin
    // Initialize Inputs
    clk = 0;

    // Wait 100 ns for global reset to finish
    #100;

    // Add stimulus here

end

always begin
#5 clk = 1 ; #5 clk =0;
end

endmodule

now when i use ISE simulation mode .

the waveform is like :

enter image description here

to get the proper waveform i first set the time .

then click the "restart" button and then "run for the time specified in the toolbar " .

why the out put is still X after several cycles of the clock ?

does it have anything to do with the comment " Wait 100 ns for global reset to finish"

(i also tried running the counter for 120 ns but got the same result .)

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The initial value (at time 0) of the reg type in Verilog is X. At the first posedge of clk, 1 is added to X, which results in X. So, the out signal remains at X throughout the simulation. You have two choices:

  1. Initialize out in an initial block (to 0, for example), or

  2. Use a reset signal to initialize out

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  • \$\begingroup\$ I also initialized out to 0 in the initial block . then i had to define out as a reg in the testbench . It got value 0 even when i ran the simulation till 120ns . \$\endgroup\$ – kiyarash Dec 9 '15 at 14:29
  • \$\begingroup\$ @kiyarash: Is the initial block inside your my_counter module? Update the code in your question with this new information so that others can reproduce your results. \$\endgroup\$ – toolic Dec 9 '15 at 14:41
  • \$\begingroup\$ I also tried adding a reset signal and it worked . I first initialized reset to 1 then changed it to 0 . \$\endgroup\$ – kiyarash Dec 9 '15 at 15:17
  • \$\begingroup\$ I'll update my code asap \$\endgroup\$ – kiyarash Dec 9 '15 at 15:18
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Here is something basic that i would like to share is the initial value of the Counter register is not zero by default it is xx since counter itself is made up of flipflops which have three states 0, 1 and x. For your code to work you need to add a reset signal which would reset the counter register and set it to initial value as zero

modify the design according to this code snippet:-

    ////////////////////Code snippet start
    always @ (posedge clk or posedge rst) 
    begin
      if(rst)
        counter <= 4'd0;
      else
        counter <= 4'd1;
    end
    /////////////////Code snippet end

modify the test bench according to this code snippet

    //////////////////Code snippet start
    initial begin
    clk = 0;
    rst = 0;
    #10
    rst = 1;
    #17
    rst = 0;
    end
    //Code snippet end

also it is a good practice to generate the clock as shown below in a separate initial begin block

    //////////Code Snippet start
    initial begin
    always #5 clk = ~ clk;
    end
    ///////////Code Snippet end
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