I am using ISE to write my first verilog code .
i wrote a counter :
`timescale 1ns / 1ps module my_counter( input clk , output reg [3:0] out); always @(posedge clk) begin out <= out+1 ; end endmodule
then used ISE to make a testbench (added clk myself!) :
`timescale 1ns / 1ps module mycounter_test; // Inputs reg clk; // Outputs wire [3:0] out; // Instantiate the Unit Under Test (UUT) my_counter uut ( .clk(clk), .out(out) ); initial begin // Initialize Inputs clk = 0; // Wait 100 ns for global reset to finish #100; // Add stimulus here end always begin #5 clk = 1 ; #5 clk =0; end endmodule
now when i use ISE simulation mode .
the waveform is like :
to get the proper waveform i first set the time .
then click the "restart" button and then "run for the time specified in the toolbar " .
why the out put is still X after several cycles of the clock ?
does it have anything to do with the comment " Wait 100 ns for global reset to finish"
(i also tried running the counter for 120 ns but got the same result .)