0
\$\begingroup\$

I'm trying to understand how JK and D flip flops work. I am generally very airy when it comes to these topics and was hoping someone could explain in layman's terms how these two circuits work.

It is my understanding that a JK flip flop takes two inputs, j and k, returns two outputs, q and not q, and a(n) (inverted?) clock signal. I read here, http://forum.allaboutcircuits.com/threads/jk-and-d-flip-flops-which-one-to-choose.32024/, that it has four functions: SET, CLEAR, HOLD, or TOGGLE.

Likewise, D flip flops take one input, d, returns two outputs, q and not q, and inputs a clock signal. They only have the two functions SET and CLEAR.

What does it mean when a flip flop performs a function like SET, CLEAR, HOLD, or TOGGLE? Does this alter output? Current state? How? Why?

When attempting to follow a circuit that implements both, I start with a clock signal that goes into each flip flop. From there, I really have no clue how to trace what's going on.

As an example, the clock signal first enters JK flipflop, then D flipflop. The Q for the JK flipflop returns an output, and the not Q is then input as D in the D flipflop. The Q for D flipflop then becomes an output, and the not Q gets input into the J and the K (I'm assuming with a new clock signal, which essentially restarts the whole process) of the JK flipflop.

I would like trace the output and current state for each time the process repeats. Ultimately, I am trying to determine the "transitions" between each state. I see multiple examples on other websites, but all use different variables representing different things and it throws me off huge.

Any help explaining these complicated buggers is appreciated!

\$\endgroup\$
  • \$\begingroup\$ Flip flops don't "return two outputs"; they are referred to as having one output and its complimentary, because they are only ever the opposite of each other. Admittedly plenty of flip flop ICs provide two physical pins, for Q and notQ, but that's just for convenience. The flip flop itself only has one output. \$\endgroup\$ – CharlieHanson Dec 9 '15 at 14:04
1
\$\begingroup\$

"What does it mean when a flip flop performs a function like SET, CLEAR, HOLD, or TOGGLE?"

    first I'll like you to explain about latches.There is not much difference between latches and flipflop.Latches don't have clock input but flipflop have clock inputs.Here is a simple Set-Reset latch
      SR latch.
      Explanation for SET:From the name,it suggests that,when you apply Logic HIGH to 'S'(Set),this sets the output Q to logic HIGH.The not(Q) will be it complement(logic LOW)
    .
      Explanation for RESET:If you apply logic HIGH to 'R'(Reset),it makes the output Q to logic LOW,then not(Q) will be HIGH.(note that 'S' should be in logic LOW at that time).
      Explanation for HOLD:If you apply Logic LOW to both input(S and R),The output doesn't change.I mean,it HOLDS the past output.
      Explanation for TOGGLE:If you apply both pins with logic HIGH,it leads to indeterminate state for SR latch and it's the limitation of SR latch,so if you consider J-K flipflop,when you apply both J and K with Logic HIGH,it changes the output(ie. output HIGH goes to LOW and vice versa).This is called as TOGGLING.

      "I start with a clock signal that goes into each flip flop. From there, I really have no clue how to trace what's going on."

    Please note that,clock signal is to activate the latch circuit.A Latch with Clock pulse is called as Flipflop.Applying clock signal to activate a latch is called as Triggering.There are two types of triggering.One is edge triggering and the other is level triggering.
clock.In level triggering,The flipflop is ready to get the input throughout the Level of the clock continuous.In edge triggering,The flipflop will be ready to get input only when the edge of the clock is detected.Always edge triggering is preferred.

\$\endgroup\$
  • \$\begingroup\$ Can you please edit you question with the schematics which you explained in your question. @kill4silence \$\endgroup\$ – Aadarsh Dec 9 '15 at 15:56
0
\$\begingroup\$

You seem to try to understand these all at once no wonder you get confused ! Start here and try to understand how each flip-flop works before looking at the next (more complex) variant.

All flip-flops have a lot in common and they're less different than you think. The J-K flipflop is more complex because it can be configured to behave like almost any of the other flip-flops.

Indeed if you look at many different sources you will get confused because not everyone names the signals and states in the same way. So PICK ONE and continue from there. When a designer uses a specific flip-flop it is always the datasheet for that particular flip-flip which matters. Only the datasheet describes the behavior, you cannot assume any other description found elsewhere to be correct.

Personally I only look at the truth table for any flip-flop, a proper truth table reveals everything. And here is an example of a proper datasheet for a JK flip-flop you can buy in a chip !

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.