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enter image description here I was going thru the datasheet of Micron SPI Flash. The timing diagram has tCHSL : S# not active hold time (relative to CLK)

What exactly is this? According to the timing diagram, this is measured between rising edge of clock and S# going high to low.

But this never happens. Clock is 'off' when S# is High.

Figure 3 in "AC Characteristics" in link below -

www.micron.com/.../{0F7AD04B-73A4-45FA-A2A0-B19F77B3A42B}

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SPI buses are frequently shared with multiple devices. So the clock might be running while device A is deselected, because another device B is selected.

The timing constraint tCHSL described is the time S# must be held high after a rising clock edge. This might happen if devices are rapidly switched. If this constraint is broken, device A might behave as if the last clock edge for device B was directed towards itself or generally experience undefined. It's a pretty unlikely case and most datasheets will have only a required S# low to CLK rising setup timing constraint instead with the implicit assumption that this edge case is averted by the SPI protocol itself though proper S# hold time tCHSH after the last clock edge of device B.

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