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Let's assume that we need to design Mixed signal PCB with 2 fast integrated circuits(tr_min = 1ns) operating at different voltage levels(3.3V and 4V). There are however other voltage levels on the PCB(5V, 12V) with low speed signals. Design must be done one 4 layer(i.e. sig-gnd-pwr-sig).

What voltage level should be used on PWR plane?

If i.e. PWR=3.3V then would return current path of the 4V high speed IC on bottom layer be GND or 3.3V PWR? I think it would be GND plane. So if we keep PDN in mind what Rolf says then 6 layer would be more appropriate(i.e. sig-gnd-pwr-gnd-pwr-sig). According to Olin, we could remove PWR plane and used one GND plane as a return path for each and every signal on PCB. Therefore my stackup would be(sig - local gnd/sig - gnd - sig). I see some contradiction on those two approaches.

For further discussion, if some PDN tool is used to keep impedance below some value from i.e. 0-180MHz where should decoupling capacitors be located?

There are plenty of them, more than 60-70, so it's impossible to locate all of them near and around LQFP case. Is it OK to spread rest all over the board?

What are your thoughts?

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    \$\begingroup\$ For high-speed signals, all power planes will act as a return for dynamic current if they are bypassed properly. \$\endgroup\$ – Daniel Dec 9 '15 at 21:47
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Have a ground plane. You don't need a power plane. You do need a low impedance power supply at each IC, which means stitching as many decoupling caps as required, per supply, per IC, close enough to the ICs, directly between power and ground.

Power planes are great when you have a single plane, lots of ICs using it, and want to spread out the decoupling caps. It's a total waste of a layer if those don't apply. With multiple rails, any attempt to put all the power distribution on a single layer, that you then hopefully call the power plane, will result in silly polygons that are simply wide tracks. It's much easier to route and to nail with decoupling if you simply treat it all as tracks, on the most appropriate layer, from the start.

All the return currents will flow in the ground plane. Keep the ground plane as a plane, do not cut it into a lace curtain to route other tracks on that layer (that can happen when there isn't an organised way to route tracks, and the last track or two has to cut through the ground plane)

There is a technique called Manhattan routing, which will allow you to organise point to point or mesh routing on just two layers, without tripping yourself up. Choose an east-west layer, and a north-south layer. Hop between them using vias. While you lay the board out, resist the temptation to put a sneaky track running EW on the NS layer, and vice versa, you will regret it later when you need to cross tracks.

That gives you the spare 4th layer for signal routing the signals that wouldn't fit on the Manhattan layers.

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  • \$\begingroup\$ Great answer. I could agree that for most MCU applications power planes are mostly religion. \$\endgroup\$ – Bip Dec 9 '15 at 22:51
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I suspect I'd try to lay things out such that I could split/partition the "power plane" - I don't see anything particularly sacred about keeping the whole thing one voltage, but how to do that "specifically" would depend on the layout and which parts require power where (and that would in turn feed back and influence the layout.)

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