Let's assume that we need to design Mixed signal PCB with 2 fast integrated circuits(tr_min = 1ns) operating at different voltage levels(3.3V and 4V). There are however other voltage levels on the PCB(5V, 12V) with low speed signals. Design must be done one 4 layer(i.e. sig-gnd-pwr-sig).
What voltage level should be used on PWR plane?
If i.e. PWR=3.3V then would return current path of the 4V high speed IC on bottom layer be GND or 3.3V PWR? I think it would be GND plane. So if we keep PDN in mind what Rolf says then 6 layer would be more appropriate(i.e. sig-gnd-pwr-gnd-pwr-sig). According to Olin, we could remove PWR plane and used one GND plane as a return path for each and every signal on PCB. Therefore my stackup would be(sig - local gnd/sig - gnd - sig). I see some contradiction on those two approaches.
For further discussion, if some PDN tool is used to keep impedance below some value from i.e. 0-180MHz where should decoupling capacitors be located?
There are plenty of them, more than 60-70, so it's impossible to locate all of them near and around LQFP case. Is it OK to spread rest all over the board?
What are your thoughts?