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I know there are other questions on this site about decoupling, but I do not feel they accurately cover the full decision process.

I am interested in knowing the decisions that go into choosing decoupling caps. I do not mean a microprocessor with a well laid out datasheet containing proper diagrams of the capacitors, and I do not want to concern this questions with layout as decoupling in layout is separate and a huge subject.

Let us take an i7 as an example. What are the steps that one would take in choosing decoupling caps? Certain things in the datasheet to model? ESR models? Signal speeds? I am just curious what rabbit holes I should go down if I want to be diligent and not rely on the manufacturers recommendations (which I am aware are important).

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  • \$\begingroup\$ What is "i7"? Decoupling caps are important but just follow the DS and don't make a big deal over something that is or should be a fairly trivial exercise. It may not be trivial if one considers some strange situations i.e. there are always exceptions but you don't appear to be alluding to anything out of the ordinary. The most important thing on decoupling at HF is not using a cap that sereis resonates at too low a frequency. \$\endgroup\$ – Andy aka Dec 9 '15 at 22:33
  • \$\begingroup\$ @Andy aka - Definitely agree it can be trivial, but I want to think about this from a best practices point and plan for the worst. And apologies, I should have put Intel core I7 \$\endgroup\$ – mcmiln Dec 9 '15 at 22:38
  • \$\begingroup\$ Nothing wrong with a little bit of overkill on caps - it's just that I don't see any issue here - use what the DS says and employ good layout practises. \$\endgroup\$ – Andy aka Dec 9 '15 at 22:41
  • \$\begingroup\$ A high-end chip like a microprocessor or FPGA is likely to have substantial in-package decoupling. But they won't tell you the details of what they provide. So you're pretty much stuck with the datasheet recommendations to know what to do. The positive side is, usually you're only responsible for very low-frequency high-value bypassing where placement location is not critical. \$\endgroup\$ – The Photon Dec 9 '15 at 23:40
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The decoupling capacitor removes noise on the power rail. It also functions to shunt high frequency currents (bypass the load). We want to damp the transient response to reduce ringing and ripple.

At it's heart, this boils down to impedance matching... good 'ole Z=R+j(ωL-1/ωC). Here ω is the angular frequency of your noise, L is inductance due to PCB traces and/or switching power supply inductance, and C is the load capacitance (which you increased by introducing your decoupling cap). Low ESR parts don't contribute much to the R part, which is desirable.

If you want to go down the rabbit hole, you could determine the optimal values by using a spectrum analyzer to determine the frequency response and choosing C accordingly. This is important for antenna and RF stuff, and usually not so important for power supply filtering.

The size of the capacitor(s) depends on the frequency of noise. Ideally, you would decouple with several capacitors of varying size. You may target a certain frequency response. In high noise environments such as automotive applications, it is common to use a common mode choke. Take a look at this article and this article for more information.

Most of the time it's appropriate to haphazardly slap down a ceramic SMD low ESR 100nF, and maybe do a parallel 10uF.

Since you specifically mentioned i7... you could try to eliminate j at the CPU clock speed and your RAM speed (DDR?).

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