# How to stretch ON time of a pulse train when keeping the periods unchanged?

I'm receiving varying frequency pulse train with very short ON time and I want to convert these to pulses with longer ON time but without changing the pulse periods. On time is now around 100us. Pulse period varies between 1000us and 2500us.

The flipflop halves the frequency and skips one rising edge which I dont want in this case.

How can I achieve this Duty cycle doesn't have to be fixed just the frequency of the pulses should remain the same.

• Maybe a 555 timer as one-shot? Commented Dec 10, 2015 at 11:34
• Possible duplicate of Duty cycle adjustment for a pulse train in LTSpice? Commented Dec 10, 2015 at 11:55
• Sample it in a microcontroller and pulse-stretch in software, based on the micro's measurement of the previous period.
– user16324
Commented Dec 10, 2015 at 12:10
• no one answered it Commented Dec 10, 2015 at 12:12
• can the output be delayed one pulse time or must the leading edge of the On pulses in the output immediately follow those in the input? Commented Dec 10, 2015 at 14:30

You want something called a one shot. Basically, you ignore everything except rising edges of your input signal. You copy the rising edge to the output, but make up your own falling edge.

A one shot is a timing component that does exactly that. You can set one up so that when a rising edge comes along, it starts a timed pulse. Since your pulses vary from 1 to 2.5 ms, 500 µs is the optimal time for guaranteeing the longest minimum level time.

Without prediction or delay, you can't make a square wave output.

• so basically the pulse periods will remain the same with a duty cycle between 40% and 60%? Commented Dec 10, 2015 at 11:54
• precision of duty cycle is not important but pulse freq is important for my application. Commented Dec 10, 2015 at 11:56
• @jju: Huh? I have no idea where you got 40 and 60% from. The calculation is very basic. At 500 us on time and a period from 1 to 2.5 ms, the duty cycle is 0.5ms/2.5ms = 20% to 0.5ms/1.0ms = 50%. How is this not obvious? Commented Dec 10, 2015 at 12:01
• i think didnt get your explanation. %40 to %60 is the duty cycle Im aiming without changing the pulse frequency. it was not a calculation, i forgot to mention. so in your method will the on time be always 500us?? Commented Dec 10, 2015 at 12:04
• some wrote "dont mess with timers" in my previous questions. thats why i was a bit cautious using timers for this application Commented Dec 10, 2015 at 12:56

I believe what you describe is a monostable circuit. You can check the monostable multivibrator for reference.

What it does is starting a fixed duration pulse at every rising (falling) edge of the input. You can tune it to your liking, as long as the 'on' time does not exceed the period of the signal (consider also the transition time). You are basically creating a pwm this way.

• okay but i implemented it in LTSpice. whatever I choose rc combiantion i get the following plot: postimg.org/image/pk4tnqu3v Commented Dec 10, 2015 at 16:07

I would try using a CD4046B and use the type II phase detector. Both phase detectors use the leading edge of the input, but as your signal spans more than an octave, the type I detector may lock at the wrong frequency.

In addition, a type II phase detector is insensitive to input duty cycle, provided the input pulse width is long enough.

This would, admittedly, be a bit more difficult to implement than Olin's suggestion (which has the advantage of simplicity), but there is an application note available.

Much depends on the rate of change of frequency of the signal, though.

If that works, you will have a 50% duty cycle.

• I have no idea how to use this IC. My input pulses are around 8V amplitude, On time is now around 100us. Pulse period varies between 1000us and 2500us. How would you draw it? Commented Dec 10, 2015 at 12:10
• Have you used PLLs before? That would determine how I answer. Commented Dec 10, 2015 at 13:14
• no never used:( Commented Dec 10, 2015 at 13:15

Try passing the signal to a NOT gate. The period of the pulse train will remain the same and you will end up with larger ON time.

• then again you would have really small OFF time. Is that acceptable for your application? Commented Dec 10, 2015 at 11:26
• No the duty cycle should be around 50%. Commented Dec 10, 2015 at 11:38

One way to do this is using:

• An edge-triggered flip-flop with asynchronous reset
• A delay circuit (could just be an RC filter, possibly followed by a schmitt trigger).

configured as follows:

simulate this circuit – Schematic created using CircuitLab

The delay time will define the output high pulse width, so it needs to be selected to be narrow enough to not interfere with the next period, but wide enough to be detected.

There are probably already ICs that contain this circuitry, but I'm more familiar with IC design, so this solution is the first one that came to my mind.

This solution uses a microcontroller, although it also could be done with hardwired logic as well (probably a good application for an FPGA).

Set up an interrupt so it will trigger on the rising edge of the input signal. The uncertainty of the timing will then be half of one instruction cycle, typically in the tens of ns or less. An input capture module could also be used.

It is assumed that this interrupt, and the three timer interrupts discussed below, are the only ones in the system so the latency is fixed in each case.

Call this first interrupt time A. In the interrupt routine, capture the time from a free-running clock, and set a timer to interrupt at A + 2500 µs. Call that A'. The 2500 µs figure is chosen to be at least as long the maximum distance between pulses.

The leading edge of the next 100 µs pulse B is then acquired in the same fashion. (This also starts the cycle for the next pulse, overlapping the first, so two overlapping timers are required, which are used alternately.)

A second timer is set to interrupt at A' + (B - A) / 2, i.e. half the previous period. Call that a'.

When the interrupt for timer A' occurs, set the output high. When the interrupt for timer a' occurs, set the output low. Since both of these are being handled by interrupts, the overhead for both will be the same and the relative time between the two equal to exactly a' - A', half the time between B - A, or a 50% duty cycle.

• is there a delay? Commented Dec 10, 2015 at 17:55
• @jjuserjr Yes, there is a fixed delay of 2500 µs (maximum period). That's why I asked the question earlier and you said it was okay. The leading edge of the pulses still all have the same relative timing. Commented Dec 10, 2015 at 18:04