This solution uses a microcontroller, although it also could be done with hardwired logic as well (probably a good application for an FPGA).
Set up an interrupt so it will trigger on the rising edge of the input
signal. The uncertainty of the timing will then be half of one instruction cycle, typically in the tens of ns or less. An input capture module could also be used.
It is assumed that this interrupt, and the three timer interrupts discussed below, are the only ones in the system so the latency is fixed in each case.
Call this first interrupt time A. In the interrupt routine, capture the time from a free-running clock, and set a timer to interrupt at A + 2500 µs. Call that A'. The 2500 µs figure is chosen to be at least as long the maximum distance between pulses.
The leading edge of the next 100 µs pulse B is then acquired in the same fashion. (This also starts the cycle for the next pulse, overlapping the first, so two overlapping timers are required, which are used alternately.)
A second timer is set to interrupt at A' + (B - A) / 2, i.e. half the previous period. Call that a'.
When the interrupt for timer A' occurs, set the output high. When the interrupt for timer a' occurs, set the output low. Since both of these are being handled by interrupts, the overhead for both will be the same and the relative time between the two equal to exactly a' - A', half the time between B - A, or a 50% duty cycle.