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I'm receiving varying frequency pulse train with very short ON time and I want to convert these to pulses with longer ON time but without changing the pulse periods. On time is now around 100us. Pulse period varies between 1000us and 2500us.
The flipflop halves the frequency and skips one rising edge which I dont want in this case.
How can I achieve this Duty cycle doesn't have to be fixed just the frequency of the pulses should remain the same.
You want something called a one shot. Basically, you ignore everything except rising edges of your input signal. You copy the rising edge to the output, but make up your own falling edge.
A one shot is a timing component that does exactly that. You can set one up so that when a rising edge comes along, it starts a timed pulse. Since your pulses vary from 1 to 2.5 ms, 500 µs is the optimal time for guaranteeing the longest minimum level time.
Without prediction or delay, you can't make a square wave output.
I believe what you describe is a monostable circuit. You can check the monostable multivibrator for reference.
What it does is starting a fixed duration pulse at every rising (falling) edge of the input. You can tune it to your liking, as long as the 'on' time does not exceed the period of the signal (consider also the transition time). You are basically creating a pwm this way.
I would try using a CD4046B and use the type II phase detector. Both phase detectors use the leading edge of the input, but as your signal spans more than an octave, the type I detector may lock at the wrong frequency.
In addition, a type II phase detector is insensitive to input duty cycle, provided the input pulse width is long enough.
This would, admittedly, be a bit more difficult to implement than Olin's suggestion (which has the advantage of simplicity), but there is an application note available.
Much depends on the rate of change of frequency of the signal, though.
If that works, you will have a 50% duty cycle.
Try passing the signal to a NOT gate. The period of the pulse train will remain the same and you will end up with larger ON time.
One way to do this is using:
configured as follows:
simulate this circuit – Schematic created using CircuitLab
The delay time will define the output high pulse width, so it needs to be selected to be narrow enough to not interfere with the next period, but wide enough to be detected.
There are probably already ICs that contain this circuitry, but I'm more familiar with IC design, so this solution is the first one that came to my mind.
This solution uses a microcontroller, although it also could be done with hardwired logic as well (probably a good application for an FPGA).
Set up an interrupt so it will trigger on the rising edge of the input signal. The uncertainty of the timing will then be half of one instruction cycle, typically in the tens of ns or less. An input capture module could also be used.
It is assumed that this interrupt, and the three timer interrupts discussed below, are the only ones in the system so the latency is fixed in each case.
Call this first interrupt time A. In the interrupt routine, capture the time from a free-running clock, and set a timer to interrupt at A + 2500 µs. Call that A'. The 2500 µs figure is chosen to be at least as long the maximum distance between pulses.
The leading edge of the next 100 µs pulse B is then acquired in the same fashion. (This also starts the cycle for the next pulse, overlapping the first, so two overlapping timers are required, which are used alternately.)
A second timer is set to interrupt at A' + (B - A) / 2, i.e. half the previous period. Call that a'.
When the interrupt for timer A' occurs, set the output high. When the interrupt for timer a' occurs, set the output low. Since both of these are being handled by interrupts, the overhead for both will be the same and the relative time between the two equal to exactly a' - A', half the time between B - A, or a 50% duty cycle.
