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My VHDL design contains a FIFO generated by Coregen from Vivado 15.3. I try to debug the design with a ZeroDelay simulation. But the core is not Zerodelay and makes short changes (much shorter that a clock cycle - second signal in Image 1).enter image description here This is no problem for the function, but makes it hard to debug. If I zoom out, I can not see any more if the value stays the same or changes.enter image description here

Is there a way to force the core to act as zero delay?

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Probably not, but it's easy enough to add a register to your testbench that captures the output of the FIFO only at the relevant clock edges, and monitor the output of THAT for changes.

In addition, this would be the first step toward building a completely automatic monitor for that output that doesn't rely on visual inspection. As your design grows, you will appreciate the value of such monitors.

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