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I am confused by the concept of byte offset. In my textbook the examples always show the word aligned byte offset as being two bits but doesn't really explain how they arrive at that value. It says they are word aligned so the offset is 2 bits. This doesn't really make sense to me because I thought words were 32 bits so wouldn't the offset have to be larger than just 2?

Branching off of this, what exactly is the difference between word addressable and byte addressable and how do I calculate their respective offsets?


I have a problem that I am trying to work through that deals with all of these things. I am trying to calculate the tag, set, block offset and byte offset for a direct mapped cache. The data is 32 bits long. The cache is byte addressable and each access returns a single byte. Each line in the cache holds 16 bytes.

Here is what I have so far:

I think there are zero set bits because its direct mapped. I think byte offset is also zero because it returns 1 byte and \$log_2 1=0\$. I think block offset is 4 because each block is 16 bytes and \$log_2 (16) = 4\$

So In this case I think I would have [tag = 28 bits][index = 0 bits][block offset = 4 bits][byte offset = 0 bits] but I'm not sure.

Am I on the right track??

Thank you!!

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    \$\begingroup\$ When you are using word-aligned addressing the last two bits of the address are the bytes within the word (0-3) and so are not used. I don't understand the rest of this question. \$\endgroup\$ – Daniel Dec 10 '15 at 15:54
  • \$\begingroup\$ Okay, thank you. Why exactly is it only 2 bits? I thought words were 32 bits so wouldn't you need at least 5 bits to show this? \$\endgroup\$ – Indigo Dec 10 '15 at 16:06
  • \$\begingroup\$ You're not addressing bits but bytes, 32 bit -> 4 bytes -> 2 least significant bits of the address are not used. \$\endgroup\$ – Arsenal Dec 10 '15 at 16:11
  • \$\begingroup\$ This has nothing to do with electronics. \$\endgroup\$ – pipe Dec 10 '15 at 16:15
  • \$\begingroup\$ Oh, so if it says that memory is byte addressable and the addresses are 32 bits, that's actually 2^128 bits of info not 2^32? \$\endgroup\$ – Indigo Dec 10 '15 at 16:16
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To understand the difference between byte- and word-addressable, understand that a byte is always 8 bits, while a word may differ from system to system. Take, for example, an 8-bit system with 2 byte words. The instruction size is one word, but the bandwidth of the system is only 1/2 word. The system must be byte addressable so that it can load the instruction 1-byte at a time. It cannot be word addressable because it cannot handle a full word of data at a time. In this system, the byte offset would only be 1 bit, to choose between the first or second byte in the word.

I would like to help with the cache addressing but it's been a while and those are very detail oriented calculations. Best of luck!

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A four-byte word's bytes can be numbered 0, 1, 2, and 3. In binary, these values fit into two bits: 00, 01, 10, 11.

If a four byte word is aligned, then its byte address in memory is an integer divisible by four. This address has a binary representation ending in 00: XXXX....XXXX00. The addresses of the four bytes within the word are ...XXX00, ...XXX01, ...XXX10 and ...XXX11. In other words, the binary encoding of the offsets 0, 1, 2 and 3 fits into the least significant two-bit fields: these offsets can be expressed without changing any of the other bits in the address.

Hence "two bit offset".

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