I am trying to implement a 32-tap filter on an FPGA, I can have only 16-bits for the coefficients, and 16bits for the input samples, and my output should also be 16 bits. Multiplying a 16bit coefficient with a 16bit input sample would produce a 32bit result, and adding all the 32 taps would result in 37bits at the output. So how is it possible to get 16bit output?
Rescale it. The filter coefficients should be picked so that they all add up to the 16 bit max value. This should make the max value after the multipliers fit in to 32 bits. Then just truncate the 16 LSBs. In other words, use output[31:16] as the output and pick the filter coefficients do this does not overflow.