So i'm trying to understand this D type Positive Edge Flip Flop:
I'm having problem understanding why it's a Positive Edge triggered and not Level triggered.
I understand that when the clock is 0, NAND 2 and 3 will both output 1 locking the current values of the SR latch on the right.
but when the clock value is 1, it stop affecting the circuit , so it can be simplified into something like:
where the circuit will start to be affected by the input of D according to the previous state of the circuit.
But if this is how this D type flip flop works, wouldn't it be a level triggered flip flop instead? since the input D will affect the Set and Reset values of the SR latch on the right as long as the clock is 1.
Can someone explain where I've gone wrong in my understanding?