I'm trying to understand this D type positive edge flip-flop:
simulate this circuit – Schematic created using CircuitLab
I'm having problem understanding why it is positive edge triggered and not level triggered.
I understand that when the clock is 0, NAND 2 and 3 will both output 1 locking the current values of the SR latch on the right.
When the clock value is 1, it stops affecting the circuit so it can be simplified into something like:
Where the circuit will start to be affected by the input of D according to the previous state of the circuit.
If this is how this D type flip flop works, wouldn't it be a level triggered flip flop instead? The input D will affect the set and reset values of the SR latch on the right as long as the clock is 1.
Can someone explain where I've gone wrong in my understanding?