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Memory bandwidth for DRAM like DDR3-1600 / PC-12800 is a function (product) of memory frequency (1600 MHz) and memory bus characteristics (width and number of channels). But memory also has timings (for example, 11-11-11, measured in cycles). So is it true that the value of memory bandwidth (12800 MB/s) is unreachable unless timings for that memory equal 0 (zero), that is unreal?

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  • \$\begingroup\$ You know that you can read from banks interleaved? \$\endgroup\$
    – PlasmaHH
    Dec 12 '15 at 21:21
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    \$\begingroup\$ Also, a DRAM row is quite large compared to the bus size: anandtech.com/show/3851/… so once you've waited for the CAS select and RAS precharge, you can read out the whole row in a burst at full bandwidth. \$\endgroup\$
    – pjc50
    Dec 12 '15 at 22:08
  • \$\begingroup\$ I believe that in modern processors pages are normally read in a burst mode. During the burst read, the bandwidth is as advertised. But setting up a page read has some overhead. \$\endgroup\$
    – mkeith
    Dec 12 '15 at 22:09
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Well, you're never going to get that exactly. That's the theoretical max bandwidth. However, you can get pretty close. DRAM is set up so that rather large blocks can be read out sequentially with no wait states. Well, you might need some wait states to set it up and a few to move to the next block, but within the block it will transfer at the full rate. Generally your CPU will read or write a whole cache line at once anyway, not just a couple of words. This is a tradeoff between sequential access and completely random access, but it usually works well because a good portion of memory reads and writes are sequential.

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  • \$\begingroup\$ Also called "Burst Access" or "Burst Mode". \$\endgroup\$ Dec 13 '15 at 1:39

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