How would you find the number of clock cycles it takes to produce sum, the carry out, and overflow flag using ripple carry or lookahead adder.

Can someone please explain me how would we go on finding the clock cycles, thanks in advance.

  • \$\begingroup\$ How about 1)You determine how many gate levels your functions take, 2) what the delay per gate level is, and 3)find out your clock period. Multiply 1 by 2, and divide by 3) and round up. \$\endgroup\$ – WhatRoughBeast Dec 13 '15 at 5:10

Ripple carry and carry lookahead adders are combinatorial circuits - they do not hold state and they are not clocked. So counting clock cycles is meaningless, unless perhaps you are talking about some sort of a pipelined implementation. Generally the whole point of using something like a carry lookahead adder is that the addition operation will be completed within a single clock cycle. With registers feeding the inputs and capturing the outputs, the question becomes one of what's the fastest clock at which the adder will work. To calculate this, all you have to do is find the worst-case propagation delay along the worst-case critical path and factor in the setup time and clock to output delay of the registers.

Note that it is also possible to treat an adder (or any other combinatorial logic for that matter) as a multicycle path. This means that the input will be held constant for N clock cycles, and the output will be captured on the last clock cycle. This allows the clock to run faster than the logic, at the expense of adding wait states. This is inferior to pipelining as in a pipelined setup, you can get a new result every clock cycle with a latency of one clock cycle per pipeline stage. However, it can be difficult to pipeline certain logic functions and pipelining does require inserting extra registers which will consume more area, power, etc.


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