I'm routing a 4-layer PCB with a DP83640 chip on it. The layer stack is signal-GND-PWR-signal. The datasheet recommendate use bead or 0 Ohm resistor to isolate the VDD.
6.4 Power Supply Recommendations The VDD supply pins of the device should be bypassed with low impedance 0.1-μF surface mount capacitors. To reduce EMI, the capacitors should be places as close as possible to the component VDD supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding EMI beads becomes necessary to meet system level certification testing requirements (see Figure 6-17). It is recommended the PCB have at least one solid ground plane and one solid VDD plane to provide a low impedance power source to the component. This also provides a low impedance return path for non-differential digital MII and clock signals. A 10.0-μF capacitor should also be placed near the PHY component for local bulk bypassing between the VDD and ground planes.
Because there multiple VDD pin for the chip, so the easies way is to split the power plane. But then I will have signal wires crossing the slots :). I don't think it's a good idea.
Any good suggestions?