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I'm routing a 4-layer PCB with a DP83640 chip on it. The layer stack is signal-GND-PWR-signal. The datasheet recommendate use bead or 0 Ohm resistor to isolate the VDD.

6.4 Power Supply Recommendations The VDD supply pins of the device should be bypassed with low impedance 0.1-μF surface mount capacitors. To reduce EMI, the capacitors should be places as close as possible to the component VDD supply pins, preferably between the supply pins and the vias connecting to the power plane. In some systems it may be desirable to add 0-Ω resistors in series with supply pins, as the resistor pads provide flexibility if adding EMI beads becomes necessary to meet system level certification testing requirements (see Figure 6-17). It is recommended the PCB have at least one solid ground plane and one solid VDD plane to provide a low impedance power source to the component. This also provides a low impedance return path for non-differential digital MII and clock signals. A 10.0-μF capacitor should also be placed near the PHY component for local bulk bypassing between the VDD and ground planes.

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Because there multiple VDD pin for the chip, so the easies way is to split the power plane. But then I will have signal wires crossing the slots :). I don't think it's a good idea.

Any good suggestions?

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  • \$\begingroup\$ A split power plane is not a big deal if there is a solid ground plane. More on that in a bit. \$\endgroup\$ – Matt Young Dec 16 '15 at 3:47
  • \$\begingroup\$ Don't split the plane for this. Routing high-speed signals across a plane split is much worse for EMI than not having the ferrite beads. If needed, you can put an optional 0-Ohm on every power pin (to avoid splitting). This means you will need to place two components close to every power pin instead of just one. If you have space, go ahead and do it. Otherwise, I would omit the bead altogether before I would split the plane. \$\endgroup\$ – mkeith Dec 16 '15 at 5:08
  • \$\begingroup\$ Somewhat related: electronics.stackexchange.com/questions/15135/… and please do not split your planes, if you properly route your signals splitting the plane doesn't change anything. \$\endgroup\$ – Vladimir Cravero Dec 16 '15 at 9:05
  • \$\begingroup\$ You should read the thread Vladimir linked to. It does not agree exactly with the advice I am giving, but also does not suggest splitting the plane. Olin's answer is interesting, and I don't think a lot of people are in that same school of thought, but I would definitely give his answer and comments a good read. \$\endgroup\$ – mkeith Dec 18 '15 at 18:47
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Do not split the plane. The datasheet is suggesting that each pin be provided with a highly localized RC or LC filter. In other words, you place one R in series and one C in shunt very close to each VCC pin on the device.

It says nothing about splitting the plane. There is zero chance that splitting the plane will help you with EMI, and it will probably make it worse.

If you create a "local plane" fed with a ferrite (which is really just an inductor) and put a lot of capacitance on that local plane, you are, in essence, designing a patch antenna. If the VCC current demand happens to be near the resonant frequency of your patch antenna, you will have big EMI problems.

The only reason to split planes is to protect victim signals. It never provides any benefit to the aggressor signal or EMI.

Quote from the datasheet: "It is recommended that the PCB have at least one solid ground plane and one solid VDD plane to provide a low impedance power source to the component."

I added the emphasis.

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I would not split the ground plane, but I see no issues with creating a local plane for the device.

Find a ferrite that can handle the current required (they are usually available in the same package sizes as resistors), and put that down as a single power entry to the device. On the device side have a solid plane with this power and keep the ground plane solid. Route the high speed signals on layer 1 to maintain a constant reference to ground if possible (avoids routing over the split).

Logically, it is something like this:

Feeding power through a ferrite

It is not at all unusual to use this approach and provided you take care with the signals you care about (high speed ones) it should be successful.

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  • \$\begingroup\$ Yes, I'm considering this method too, I'm trying to move all my signals routed to this chip to the top layer, which is referenced to the ground plane. \$\endgroup\$ – diverger Dec 16 '15 at 9:14
  • \$\begingroup\$ Is it suitable to put high-speed signal vias on the local plane? Because I can't totally avoid vias on high-speed line, but I just put them on the local power plane, there is no vias on the high speed line outside the local power plane. \$\endgroup\$ – diverger Dec 16 '15 at 9:39
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    \$\begingroup\$ The datasheet very clearly states that you should use a bead for each pin, and says NOTHING about splitting the plane. In fact it suggests that you should have one solid VCC plane. What you want to do is provide the lowest impedance return path possible for all signal currents. Splitting the plane can never reduce impedance. It can only increase it. I would also like to point out that ferrite beads are actually inductors. So if you run VCC through a ferrite, and then put a bunch of capacitors on there, you are building a resonant circuit. You might want to calculate the resonant freq. and Q. \$\endgroup\$ – mkeith Dec 16 '15 at 23:29
  • \$\begingroup\$ @mkeith: You are right, can you provide some materials or links about how to choose ferrite beads considering the decouple capacitors. \$\endgroup\$ – diverger Dec 17 '15 at 11:47
  • \$\begingroup\$ Well, there are several concerns. First DC resistance must be low enough so that it does not cause a large voltage drop. Second, the impedance at the frequency you wish to suppress must be high enough to help with that. Lastly, when you calculate the LC resonant frequency, it should occur at a location on the ferrite impedance graph where the ferrite is very lossy. This will insure that resonance is spoiled by low Q. Ferrite inductance is usually not given. You have infer it from the impedance chart. \$\endgroup\$ – mkeith Dec 18 '15 at 18:42

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