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QUESTION

Are interface parameters for a module automatically deducted from the interface instance that is connected to the module instance?

Background

I am designing a System that provides a communication infrastructure with multiple channels. Each channel can be tied to a different module by the user. To separate the user logic from the system I created a module wrapping the infrastructure. This is the setup in (pseudo) code

interface channel_if #(parameter int CHANNELBITS = 8);
     logic dummy;

     modport arbiter(input dummy);
endinterface

module arbiter(
    channel_if.arbiter channel[CHANNELS] //MODPORT defined
);
endmodule

module infrastructure(
    channel_if #(CHANNELBITS=16) channel[CHANNELS] //PARAMETERS defined
);

arbiter channelArbiter(channel);

endmodule

The problem I have is the following: I can either specify the parameters for the interface array OR the modport. I found no way (Vivado 2015.1) to define both, parameters AND modport.

In top the following code would be found:

... channel_if #(CHANNELBITS=16) channelHarness[CHANNELS]; channel_if channelHarness[CHANNELS]; //either this or previous

infrastructure(.channel(channelHarness.arbiter)); ...

While it is no problem to assign InterfaceArray.modport to the infrastructure module, I can not assign InterfaceArray.modport inside infrastructure (We already stripped the interface array down to modports at the infrastructure module boundary).

Questions

Since I can not define the interfaceparameters for arbiter (only possible if I do not define the modport, which yields inout orts for the interfac,e which I do not want), can I use Interfaces with non defaultparameters?

Are interface parameters for a module automatically deducted from the interface instance that is connected to the modelinstance?

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Parameter values are deduced from the interface instance that is connected to the model instance. See the example in section 25.8 Parameterized interfaces of the 1800-2012 LRM.

The interface/modport construct in the SystemVerilog language is one of the most poorly documented sections of the LRM and has many open issues. I would avoid using them unless absolutely necessary.

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  • 1
    \$\begingroup\$ I will read this, as "there is no way to specify both explicitly". It is a shame that interfaces are so "buggy", since they were one of sstem verilog strongpoints, leading me to try out system verilog. \$\endgroup\$ – ted Dec 22 '15 at 16:54

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