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USB 3.0 has been around for quite some time, since it was released in 2008. But you don't see any simple microcontrollers with an internal peripheral that can do USB 3.0.

The Atmega32u4, a simple 8-bit AVR, has an embedded USB2.0 phy inside and only runs at 16MHz, as such it is obviously too slow to do USB3.0. Although there are Cortex-M controllers running at over 200MHz that don't have a USB3.0 peripheral! At this point, I feel like the clock for the MCU no longer matters. The lowest end processor I can find that does USB 3.0 is TIs Keystone MPU with an ARM-A15

Is it just taking a considerable amount of time to create the IP for lower end MCUs or does it require a clock generation (or some other) unit that isn't worth the cost to develop it for cheaper MCUs?

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    \$\begingroup\$ You mean USB3 superspeed at 4.8Gig per second signalling rates? I would say something that needs to shuffle data around that fast... USB2 is I think 480mbit or so which most µc have no ability to saturate \$\endgroup\$
    – PlasmaHH
    Dec 17, 2015 at 16:16
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    \$\begingroup\$ Most MCUs don't even implement USB 2.0 High Speed. If you read the data sheets, it will always say "USB 2.0 (Full Speed)". \$\endgroup\$
    – Simon Richter
    Dec 17, 2015 at 19:54

3 Answers 3

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USB 3.0 PHY (physical, electrical) layer achieves the 5Gbit/s transmission rate utilizing high speed differential signaling (CML), same as PCI Express. Implementation of this physical layer on chip requires a transceiver, and a SERDES (serializer, deserializer) at the minimum, in addition to the MAC (media access control) layer requirements. These blocks would probably require additional clock generation and signal conditioning circuitry (equalizers on the lines to reduce bit error rates). Putting all this circuitry in your chip has two primary costs, silicon area and power.

Even if we assume if the power consumption is irrelevant, as you can turn the whole thing off if you're not using it, shipping a MCU with a USB 3.0 PHY would probably increase the silicon area enough to increase the costs drastically.

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    \$\begingroup\$ You are correct that USB 3 uses differential signalling at high speed, but it uses CML not LVDS (as does PCIe). \$\endgroup\$
    – Tom Carpenter
    Dec 17, 2015 at 16:29
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    \$\begingroup\$ That is correct, I've corrected the answer. \$\endgroup\$
    – deadude
    Dec 17, 2015 at 17:03
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USB 3.0 operates at 5Gbit/sec. Not only does that require high-frequency clock generation, for many "microcontroller" level products it exceeds the RAM bandwidth! There's simply no point in connecting to a firehose you cannot make use of.

This TI processor with USB3 has DDR3 support, which is fast enough, and multiple >1GHz cores to actually make use of that data.

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The easiest way I have found to add USB 3.0 functionality to a design is the Cypress EZ-USB FX3™ SuperSpeed USB 3.0 peripheral controller.

http://www.cypress.com/products/ez-usb-fx3-superspeed-usb-30-peripheral-controller

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  • \$\begingroup\$ have you used this device ever at all? \$\endgroup\$
    – quantum231
    Aug 16, 2021 at 0:00

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