How can I use the watchdog timer in interrupt mode?

Question

I am using an atmega168 with avr-libc. Now, to form control loop of a fixed duration, I need a, say 1 second interrupt. Being clocked from an 8MHz clock, the only useful clock source seems to be he 128kHz watchdog oscillator.

The datasheet(page 49) hints that this is possible:

In interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be used to wake the device from sleep-modes, and also as a general system timer.

However, the library reference makes no mention of operating modes. What now?

Answer 1

The watchdog oscillator is very inaccurate, and if you look at the datasheet you'll see that its frequency varies between 111 and 121kHz depending on both temperature and supply voltage.

So while you could set WDIE and implement WDT_vect, you're much better off using a timer for this. Especially if you're using a crystal or external clock with more accuracy than the internal RC oscillator.

Answer 2

If you want an interrupt every 1 second with an 8Mhz clock, probably the best way is to use a Timer1 in CTC mode with an appropriate prescaller and TOP value.

By using the clk/1024 prescaler, you lower the rate of the counter to 8KHz from 8Mhz. You select this this prescaller with these bits...

By using CTC mode, you tell the counter to reset every time it hits the TOP. Next you can select CTC mode with these bits...

Finally, we need to set the TOP value so that it will match at 1Hz. Here is the formula for calculating the frequency generated in CTC mode...

...where N is the prescaller (1024 in our case) and F_{clk_I/O} is the IO clock (8Mhz in our case). Note that this formula gives us the frequency of a square wave that will be output if the pin toggles on each match, so We actually want double the value to get the match rate. To do this, we can just multiply by 2 (or cross out the 2 in the denominator).

After a little algebra, we (should) get a value for TOP of 7999. This makes intuitive sense since it takes one clock cycle for the counter to reset after hitting top, so if we start at zero and count up to 7,999 clock we will need one more to get back to where we started.

In the CTC mode we selected above, the TOP is held in the OCR1A register, so we set this register to 7999.

Timer1 will now fire a match at 1Hz.

Finally, we just need to enable an interrupt routine to run on each match. The interrupt is controlled by the OCIE1A bit...

Once we set this bit, our ISP should be called at exactly 1Hz (depending on the accuracy of the 8Mhz clock the chip is running from).

Answer 3

Quoted from your attached

"Bit 6 - WDIE: Watchdog interrupt enable

When this bit is written to one and the I-bit in the status register is set, the watchdog interrupt is enabled. If WDE is cleared in combination with this setting, the watchdog timer is in interrupt mode, and the corresponding interrupt is executed if time-out in the watchdog timer occurs If WDE is set, the watchdog timer is in interrupt and system reset mode. The first time-out in the watchdog timer will set WDIF. Executing the corresponding interrupt vector will clear WDIE and WDIF automatically by hardware (the watchdog goes to system reset mode). This is useful for keeping the watchdog timer security while using the interrupt. To stay in interrupt and system reset mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this might compromise the safety-function of the watchdog system reset mode. If the interrupt is not executed before the next time-out, a system reset will be applied"

It has all the information for you to set up the watchdog to operate in the timer mode by writing the correct setting to the WDTCSR register.

Table 11-1 in page 54 summarizes all the operating mode for the watchdog timer and the necessary bit settings to implement the desired mode