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Hello guys I am trying to translate following VHDL code to Verilog, however it does not work even if they look like pretty same. I get no errors however it is not working with Verilog one but works with VHDL one. Can you guys please help me to work out this problem?

VHDL Code (working)

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.std_logic_unsigned.all;
use ieee.numeric_std.all;
entity binbcd8 is

port(
b: in unsigned(7 downto 0);
p: out unsigned(9 downto 0)
);
end binbcd8;

architecture Behavioral of binbcd8 is

begin

bcd1: process(b)
variable z: unsigned(17 downto 0);
begin
for i in 0 to 17 loop
    z(i):='0';
end loop;

z(10 downto 3):=b;

for i in 0 to 4 loop
    if z(11 downto 8)>4 then
        z(11 downto 8):=z(11 downto 8)+3;
    end if;
    if z(15 downto 12)>4 then
        z(15 downto 12):=z(15 downto 12)+3;
    end if; 
    z(17 downto 1):=z(16 downto 0);
end loop;
p<=z(17 downto 8);

end process;    
end Behavioral;

Verilog code (not working):

 module binbcd8(input[7:0] b,output reg[9:0] p);
 reg[17:0] z;

 integer i;

 always@(b)
     begin
         z <=17'b0;
         z[10:3] <=b;
         for(i=0;i<4;i=i+1) begin
             if(z[11:8]>4)
                 z[11:8]<=z[11:8]+3;
             else
                 z<=z;
             if(z[15:12]>4)
                 z[15:12]<=z[15:12]+3;
             else
                 z<=z;
             z[17:1]<=z[16:0];
         end
         p<=z[17:8];
     end
 endmodule

It does not work. Can you please help me?:

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  • \$\begingroup\$ Delete the non-standard std_logic_unsigned library. The numeric_std one should be adequate and avoids possible ambiguity. Also, the first for loop is unnecessary : z := (others => '0'); replaces it with a single statement. \$\endgroup\$ – user_1818839 Dec 19 '15 at 16:46
  • \$\begingroup\$ @BrianDrummond I have no problem with vhdl my Problem is my verilog code is not working but vhdl is working by the way thanks for your advices \$\endgroup\$ – Nihad Azimli Dec 19 '15 at 17:07
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    \$\begingroup\$ @NihadAzimli I've updated the question title to match you question - you had said Verilog to VHDL in the title, but are actually trying to go the other way. \$\endgroup\$ – Tom Carpenter Dec 19 '15 at 17:10
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    \$\begingroup\$ Have you tried simulating the design? If so, can you describe what "it does not work" means. If you haven't simulated it, then you should do so. \$\endgroup\$ – Tom Carpenter Dec 19 '15 at 17:13
  • \$\begingroup\$ Please don't cross-post the same question to multiple stacks. StackExchange policy is against cross-posting. You can make a flag to the moderators to migrate a to another stack, if you so choose. \$\endgroup\$ – Nick Alexeev Feb 27 '16 at 17:04
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The variable assigment in VHDL (with :=) takes place immediately. To get the same behaviour in Verilog, you have to use the blocking assignment with = instead of the non-blocking one (<=). In your example, blocking assigments for variable z are required because your code checks the new value of z immediately after assigning it.

Moreover, the loop runs from 0 to 4 (inclusive) in VHDL. In your Verilog code, it goes from 0 to 3 because it breaks out on 4. You have to change the condition in your for statement to "less or equal" comparison:

for(i=0; i<=4; i=i+1) begin

Minor code improvements:

After changing the assigment for z to a blocking one, you can remove these else-cases, because they have no effect:

    else
      z = z

In the addition, you should add a constant with a specific length:

      z[11:8] =z[11:8] +4'd3;
      z[15:12]=z[15:12]+4'd3;

The constant 3 without a length specification has a length of 32-bit and the synthesis compiler issues a warning about truncating to 4 bits.

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