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I am trying to do parking sensor with verilog and I have its vhdl code and trying to translate it to verilog can you please help me to find out what is my problem. There is no error the error is only when I implement with vhdl one it works however it does not work with verilog one

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;


entity ultrasonic_measurer is
port(

rst   :in std_logic;
clk     :in std_logic;

time_passed_value   :OUT std_logic_vector (19 downto 0);


sig : inout std_logic


);

end ultrasonic_measurer;

architecture Behavioral of ultrasonic_measurer is


signal counter : unsigned (25 downto 0);
signal distance_counter : unsigned (19 downto 0);
signal read_value    : unsigned (19 downto 0);
signal state    :std_logic_vector(1 downto 0);
signal      sig_buf:std_logic;
signal      sig_buf2:std_logic;
signal      sig_buf3:std_logic;
signal state_pulse  :std_logic_vector(1 downto 0);
begin
time_passed_value<=std_logic_vector(read_value);



process(clk,rst)
begin
if rst='0' then
distance_counter<=(others=>'0');
counter<=(others=>'0');
state<=(others=>'0');
state_pulse <=(others=>'0');
read_value<=(others=>'0');  
    sig_buf<='0';
    sig_buf2<='0';
    sig_buf3<='0';
elsif rising_Edge(clk)then
counter<=counter+1;

case state is
when "00" =>

    distance_counter<=(others=>'0');
    state_pulse<="00";

    sig<='0';

    if counter = to_unsigned(50000000,26) then--1 s
        state<="01";
        counter<=(others=>'0');
    end if;

when "01" =>        
    distance_counter<=(others=>'0');        
    sig<='1';

    if counter = to_unsigned(1000,26) then--10 us
        state<="11";
        counter<=(others=>'0');
    end if;

when "11" =>        
    distance_counter<=(others=>'0');        
    sig<='0';
    state_pulse<="00";      

    if counter = to_unsigned(50000,26) then--500 us
        state<="10";
        counter<=(others=>'0');
    end if;

when "10" =>
    sig<='Z';

    sig_buf<=sig;
    sig_buf2<=sig_buf;
    sig_buf3<=sig_buf2;     

    case(state_pulse) is

    when"00" => --bekleme

        distance_counter<=(others=>'0');

        if sig_buf3='0' and sig_buf2='1' then --rising edge
            state_pulse<="01";
            counter<=(others=>'0');
        end if;


        --bu stepte takılı kalırsa
        if counter = to_unsigned(100000,26) then--2ms
            state_pulse<="11";
            counter<=(others=>'0');
        end if;



    when"01" =>         

        distance_counter<=distance_counter+1;

        if sig_buf3='1' and sig_buf2='0' then --falling edge
            state_pulse<="11";
            counter<=(others=>'0');
        end if; 


        --bu stepte takılı kalırsa
        if counter = to_unsigned(1000000,26) then--20ms
            state_pulse<="11";
           distance_counter<=(others=>'0');
            counter<=(others=>'0');
        end if;

    when"11" => --okuma tamamlandı.

        read_value<=distance_counter(19 downto 0);
        counter <=(others=>'0');
        state  <="00";  
        state_pulse<="00";  

    when others=>
            state_pulse<="00";
    end case;           


when others=>
    state<="00";
end case;


end if;
end process;
end Behavioral;

And my Verilog equivalent of this vhdl code is following. I cannot understand what is my error.

    module ultrasonik_measure(rst,clk,time_passed,sig);

    input rst;
    input clk;
    output reg[19:0] time_passed;
    output reg sig;

    reg[25:0] counter;
    reg[19:0] distance_counter;
    reg[19:0] read_value;

    reg[1:0] state;
    reg sig_buf;
    reg sig_buf2;
    reg sig_buf3;

    reg[1:0] state_pulse;

    initial time_passed=read_value;//pp

    always@(clk,rst)
    begin
        if(rst==0) begin
            distance_counter<=0;
            counter<=0;
            state<=0;
            state_pulse<=0;
            read_value<=0;
            sig_buf<=0;
            sig_buf2<=0;
            sig_buf3<=0;
        end
        else if(clk) begin
            counter<=counter+1;
            case(state)
            2'b00:begin
                distance_counter<=0;
                state_pulse<=2'b00;
                sig<=0;
                if(counter==26'd50000000)begin
                    state<=2'b01;
                    counter<=0;
                end
            end

            2'b01:begin
                distance_counter<=0;
                sig<=1;
                if(counter==26'd1000)begin
                    state<=2'b11;
                    counter<=0;
                end
            end

            2'b11:begin
                distance_counter<=0;
                sig<=0;
                state_pulse<=2'b00;
                if(counter==26'd50000)begin
                    state<=2'b10;
                    counter<=0;
                end
            end

            2'b10:begin
                sig<=1'bz;//deassign sig;//sig<=0;//deassign sig;

                sig_buf<=sig;
                sig_buf2<=sig_buf;
                sig_buf3<=sig_buf2;

                case(state_pulse)
                2'b00:begin
                    distance_counter<=0;
                    if(sig_buf3==2'b0 && sig_buf2==2'b1)begin//////
                        state_pulse<=2'b01;
                        counter<=0;
                    end
                    if(counter==26'd100000)begin
                        state_pulse<=2'b11;
                        counter<=0;
                    end
                end
                2'b01:begin
                    distance_counter<=distance_counter+1;
                    if(sig_buf3==1'b1 && sig_buf2==1'b0)begin
                        state_pulse<=2'b11;
                        counter<=0;
                        end
                    if(counter==26'd1000000)begin
                        state_pulse<=2'b11;
                        distance_counter<=0;
                        counter<=0;
                    end
                end
                2'b11: begin
                    read_value<=distance_counter[19:0];

                    counter<=0;
                    state<=2'b00;
                    state_pulse<=2'b00;
                end
                default: state_pulse<=2'b00;
                endcase
            end
            default:state<=2'b00;
            endcase
        end
    end     
    endmodule
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  • \$\begingroup\$ Did they both work correctly in simulation? \$\endgroup\$ – Brian Drummond Dec 20 '15 at 17:24
  • \$\begingroup\$ no it is not working in simulation with Verilog but works perfect with vhdl \$\endgroup\$ – John Down Dec 20 '15 at 17:32
  • 1
    \$\begingroup\$ Then you can display internal signals and see which ones are different, and trace the problem from there. \$\endgroup\$ – Brian Drummond Dec 20 '15 at 18:11
1
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In Verilog always@(clk,rst) is combinaional logic, not sequential. Plus in simulation it triggers in changes of clk and rst.

It should be always@(posedge clk, negedge rst). And you should not reference the clock within the always block; synthesis will consider it as asynchronous. Change else if(clk) begin to else begin

initial statements will only do assignments at time 0 and the assignment will not be continuous. Change initial time_passed=read_value;//pp to always @* time_passed=read_value;//pp. Or assign time_passed=read_value;//pp, but be aware assign can on only be applied wire so this will also require changing output reg[19:0] time_passed to output [19:0] time_passed

sig is an inout in your vhdl, but is an output reg in verilog. It doesn't match. In verilog, inout need to be a wire driven by an assign statement. For example assign sig = sig_out_en ? sig_out : 1'bz; where sig_out_en is the output driver enable control pin and sig_out is the value that will be driven when enabled. You need to update your code to reflect this.

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  • \$\begingroup\$ thank you! however you do not need to make output reg inout because it works correctly in that way \$\endgroup\$ – John Down Dec 20 '15 at 20:52

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