# 4x1 bit RAM implementation

I have a circuit about 4x1 bit RAM. I should implement this at LAB. In this case I can make this easily but I dont know which element used for what purpose. Here is the figure.

I googled it but couldn't find something useful.

1. Why we used decoder and data selector?
2. Why we used not gate?
3. What happening while changing Write/Read state?

Best regards.

• Some signal labels on the inputs and outputs of the J-K blocks might help understanding the operation. – Peter Bennett Dec 22 '15 at 3:46
• Study the diagrams until you know how each signal affects the operation of the circuit. They really show how everything works. – tcrosley Dec 23 '15 at 8:11

Brilliant! I haven't studied RAM implementation before, but this makes sense to me and is fun to learn about. Study up on J/K Flip-Flop operation; there's plenty of good resources on the web like this one:

J/K Flip-Flop Operation

You need a sequential logic element for each bit in your RAM array to store the data and hold it for later retrieval. That's why there are four flip-flops for each bit in the array. You need to choose which flip-flop you want to address using the address lines, so that's what the decoder and data selector are doing (answer to question 1).

The decoder (demultiplexer) takes the two address bits and turns it into four flip-flop select lines that address only one flip-flop at a time. It looks like this decoder output acts as the clock that tells the flip-flop when to latch the data and store it.

A gate is by nature combinational logic, meaning that it can pass/block/transform signals, but can't save data from cycle to cycle. In a combinational logic circuit, you get the same output for a given input and that behavior doesn't ever change from cycle to cycle. This is why the flip-flops are used instead. By nature, RAM is a sequential logic circuit.

Saying that a logic circuit is sequential is a fancy way of saying that the circuit has some kind of state that is preserved and/or changed from clock cycle to clock cycle. Often sequential logic circuits are made up of combinational logic circuits where the outputs feed back to the inputs and change circuit behavior from cycle to cycle (take a look at the way a J/K flip-flop works in the link above and you will see what I mean). In this case, you need to preserve state between a write cycle and a read cycle so you need a sequential logic circuit to do it. By itself, a gate can't do this (answer to question 2).

The read state is selecting (or multiplexing) the data stored in the flip-flops and making it available on the output pin when desired. The write state is loading the flip-flops with new data by using the decoder as an address-to-clock converter (answer to question 3).

This is fun stuff. I hope that you do build it in the lab to poke around and learn how it works. Thanks for posting the question!

• Thanks for answering. I can imagine clearly now . I made this at lab but somehow it didnt work, maybe because of components, I don't know. And i didn't have time for check which one is working which one is not. Even so I am happy because I understand how it works. – Emre dağıstan Dec 23 '15 at 8:31