I'm looking to build a reusable memory card for my SRAM as the cost of the chips can get up there. I'd like to be able to plug this into other projects (mainly with a W65C816S as I work with it) both with a breadboard and other PCBs.

Before I go about laying this down on a PCB I'm wondering if there is anything wrong or if there are any other suggestions. I can't really breadboard this as the memory is all surface mounted.

Memory Card by Hooka 61cdeb8a9dc2975b - Upverter

I've updated the circuit to add in buffers and bypass caps. For the data buffer to work I needed to add the direction signal to the header so there are some extra pins now. Are there any additional suggestions or comments?

Memory Card by Hooka 61cdeb8a9dc2975b - Upverter

Current circuit. I've changed the multiplexer chip to be low active. It's much faster propagation time is nice. The connector has been updates as well, so hopefully it's handling power and ground a little better. Additionally this has CE line suggestion @PeterSmith

Memory Card by Hooka 61cdeb8a9dc2975b - Upverter

  • 1
    \$\begingroup\$ I don't see any bypass caps, and using only one set of pins all the way at one edge of the connector for power and especially ground isn't great. What sort of rate where you hoping to run this at? \$\endgroup\$ Commented Dec 22, 2015 at 5:17
  • \$\begingroup\$ @Justin: I added a note on chip enables you may find useful. \$\endgroup\$ Commented Dec 24, 2015 at 16:33

1 Answer 1


The Address and CE# pins are quite heavily loaded, as are the data pins during a write. Even though only a single device is active at any time, the capacitive load of the pins is present from all devices at all times.

From the datasheet, A0 to A19 will have up to 48pF load plus any track capacitance and the data pins will have up to 64pF during write. CE# has a slightly heavier load (by virtue of driving the '38 decoder as well as all the memory devices).

That is a bit hefty (equivalent to about 40 inches of 4 thou track for the address pins and almost 60 inches of track for the data pins), so you may wish to consider Address and Data buffers. The track capacitance assumes a 4 thou PCB core to plane.

As noted, you will also need decoupling: a couple of bulk capacitors and two 100nF per device (one for each power pin as they are on opposing sides of the memory devices) would be my starting point. The decoder would probably be ok with a single 100nF part.

You may not need all of the decouplers, but if the pad positions are there, you can always choose to simply not fit the parts.

You may be ok with a single power pin (only one device will be active at any one time), but I would normally provision at least 2 if I have enough pins available.

Update: Use of CE# signal.

As the second SRAM CS signal is being gated by CE# already, it seems redundant to take it to the SRAMS as it is doing the same thing and layout can be simplified.

I would just tie off that CE# signal low at the SRAMS and use the gated and decoded CS.

This has an added benefit: as the capacitive loading on CE# has been significantly reduced, a great deal of timing uncertainty has been removed.


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