I'm designing an application with an Altera Cyclone V SoC (5CSXFC6C6U23I7N) and interfacing ADCs and DACs at 250MS/s. In the meantime, the design complexity has increased a bit and now there are timing constraint violations near the DAC interface part. This interface uses the LVDS SERDES hardware for the DDR data format. The data clock is 250MHz and hence 500Mb/s data rate. The FPGA is internally clocked at the sampling frequency, i.e. 250MHz, which should not be a problem with this speed grade I7 device.
Now the problem: There are a few registers near the DAC interface to correctly order the data bits. But there are timing violations between such registers, altough there is absolutely no logic between the registers. When looking at the path delays in TimeQuest, I see that there are some 3.5ns delay introduced by routing (interconnect). Together with the other delays, the required 4ns are not achieved anymore. When looking at the data path in the chip planner, I see that it is routed from approximately the center of the FPGA to the I/O section. After seeing this, I thought that I could just insert an additional register stage, so that the data could be retimed somewhere in the path. But the fitter simply places those registers near the output stage as well, always making the same path(s) fail.
I know that the interface itself is not a problem, as this was working perfectly well in pervious compilation runs. Resource utilization is below 5%, so there is also no problem with missing registers/ALMs. Setting the fitter effort to "aggressive" or reducing the target temperature range slightly improves the figures, but there is still negative slack in the range of 500ps to 1ns.
btw: The design as such is working even with the violations when the device is running here at room temperature. I want to have it working reliably though, so just ignoring the violations is definitely not an option.
Thanks and best regards,